Flash memory device

Details Flash memory device Flash memory device

2002-02-11

2003-09-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185330

Reexamination Certificate

active

06625062

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a flash memory device, and more particularly to a flash memory device which can accurately read data in spite of change of a load according to position of a memory cell and change of a process, and can improve operation speed of the device by reliably enabling the sense amplifier without time delay by generating an enable signal for a sense amplifier using a flash memory cell.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a flash memory device including a conventional sense amplifier and its drive circuit and
FIG. 2
depicts waveforms of each output signal according to read operation of a memory cell.
An address ADD being inputted through an address buffer
11
is inputted to an address transition detecting circuit
12
, a row decoder
14
and a column decoder
15
. The address transition detecting circuit
12
detects transition of the address and outputs an address transition detecting signal ATD. A delay circuit
13
delays the address transition detecting signal ATD for a predetermined time and outputs a sense amplifier enable signal SAEN for enabling a sense amplifier
18
. A row decoder
14
outputs a word line signal WL depending on the address signal ADD and a word line of a memory cell array
16
is selected by the word line signal WL. A column decoder
15
outputs a bit line selection signal B
1
sel to drive a NMOS transistor and a bit line of the memory cell array
16
is selected by the bit line selection signal B
1
sel. One cell is selected by outputs of the row decoder
14
and column decoder
15
, and data stored on the selected cell is inputted to an inverting terminal (−) of the sense amplifier
18
. The sense amplifier
18
compares data SAIN
1
stored on the selected cell, which is inputted to the inverting terminal (−) thereof, with data SAIN
2
stored on a reference cell, which is inputted to an non inverting terminal (+) thereof and outputs output data SAOUT. The output data SAOUT is outputted to the outside DOUT.
The flash memory device including the sense amplifier and its drive circuit configured as described above makes the access time change during the sense amplifier is enabled and outputs sensing data to an output buffer. The sense amplifier enable signal is outputted from the delay circuit which delays the address transition detecting signal. Since the enable signal is generated by delaying the address transition detecting signal, the sense amplifier outputs error data by change of a load according to position of a memory cell and change of a process.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a flash memory device which can read accurate data in spite of change of a load according to position of a memory cell and change of a process.
Another object of the present invention is to provide a flash memory cell which can improve operation speed of the device by reliably enabling a sense amplifier without time delay using a flash memory cell. To achieve the above objects, a flash memory device according to the present invention comprises:
a memory cell array having a plurality of memory cells;
a dummy cell array having a plurality of dummy cells and connected to each word line of said memory cell array;
means for applying a voltage to a bit line of said dummy cell array;
a level detector for detecting potential of the bit line in said dummy cell array;
a row decoder for selecting a word line of said dummy cell array and said memory cell array according to an address signal; and
a column decoder for selecting a bit line of said memory cell array according to said address signal;
a sense amplifier enabled by an output of said level detector and for comparing data stored on said cell of said memory cell array with data stored on a reference cell.


REFERENCES:
patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 6191979 (2001-02-01), Uekubo

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