Flash memory device

Details Flash memory device Flash memory device

2000-11-22

2002-10-29

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S401000, C257S322000, C257S320000, C257S314000

Reexamination Certificate

active

06472752

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a flash memory device. More particularly, the present invention relates to a flash memory device in which over-erase to a cell can be prevented, by prohibiting concentration of charges on a tunnel oxide film.
BACKGROUND OF THE INVENTION
In general, the erase operation of a flash memory cell is performed in sector (cell of 512K) unit. The erase operation is usually performed using F-N tunneling. If charges are accumulated within a tunnel oxide film on a source side of a specific cell, the height of barriers is lowered.
FIGS. 1A and 1B
are diagrams for explaining F-N tunneling phenomenon in a flash memory cell.
FIG. 1A
shows a F-N tunneling phenomenon in a general flash memory cell. More particularly, it shows that charges stored at a floating gate FG flow toward a source S through a tunnel oxide film
11
.
FIG. 1B
shows a F-N tunneling phenomenon in the charge-up flash memory cell. The speed of the charges that move from the floating gate FG to the source S becomes higher by positive charges
12
accumulated at the tunnel oxide film
11
. As a result, there exists a problem that over-erased cell is generated since its erase speed is higher than that of other cells in which positive charges are not accumulated at the tunnel oxide film.
FIG. 2
is a diagram for explaining a charge-up mechanism in a flash memory cell, which illustrates that charges are concentrated on the tunnel oxide film and the floating gate by means of plasma in a NMOS device.
First, the structure of a typical flash memory cell is explained as follows. A gate electrode, in which a gate oxide film, a floating gate
24
, a dielectric film and a control gate
25
are stacked on a P-well
22
formed in a semiconductor substrate
21
, is formed, and a junction
23
(source region) is formed in the P-well
22
on both sides of the gate electrode. The source region
23
and a metal line
27
are contacted through a metal contact
26
, and the metal line
27
is connected to the outside (decoder, etc.) through via hole
28
.
In this structure, etching of the via hole
28
causes positive charges and negative charges to be accumulated at the junction region
23
through the metal line
27
. At this time, as the cell shown in
FIG. 2
is a N-type, the negative charges flows into the P-well
22
and the semiconductor substrate
21
through the junction region
23
, while the positive charges are accumulated at the junction region
23
. Thus, over-erased cells are generated since the erase speed of the cell becomes higher by the positive charges accumulated at the junction region
23
. This will be explained in detail by reference to FIG.
3
.
FIGS. 3A and 3B
are a conventional flash memory cell and a layout of a cell array.
FIG. 3A
shows a layout of the unit cell, wherein a single cell is mainly consisted of a field oxide film
31
, a gate electrode
32
, a source S and a drain D.
FIG. 3B
shows a layout of a 5×2 memory cell array consisted of the unit cell as shown in
FIG. 3A. A
first source line S
1
in a cell block formed of five (5) unit cells is connected to a second source line S
2
in a cell block having the same structure to the first source line S
1
, and a common source CS line. As explained by reference to
FIG. 2
, when the via hole
35
is etched, positive charges and negative charges become conductive through the common source line CS and the metal line
27
contacted through the metal contact
34
and thus are accumulated at the common source line CS. At this time, if the cell is a N-type, the negative charges flow into the substrate while the positive charges are accumulated at the common source line CS. The accumulated positive charges are concentrated on the end (edge portion of the sector) of the common source line CS. As a result, the positive charges are accumulated at the tunnel oxide film on the source side and the floating gate of the cell. The positive charges accumulated within the floating gate are neutralized by UV light, but the positive charges within the tunnel oxide film are remained un flowed or not neutralized, thus accelerating the erase speed of the cell.
FIGS. 4A and 4B
are distribution of a rapidly erased cell in one sector of a conventional flash memory device and a graph illustrating the relationship between the amount of bit line leak current.
FIG. 4A
is a diagram for explaining the distribution of a rapidly erased cell within one sector
41
. As explained by reference to
FIG. 3
, as the positive charges conducted to the source line are concentrated on the end (edge portion of the sector) of the source line, the cells I/O-0, I/O-15 in the region other than the middle region
42
of the sector
41
are rapidly erased, thus causing over-erased cells.
FIG. 4B
shows the amount of bit line leak current per I/O when the distribution of the rapidly erased cell is same to FIG.
4
A. The graph is the case that a programming operation PGM is performed for 5 &mgr;s, an erase operation is performed for 1 ms, 2 ms, 3 ms era 1 m, era 2 m, era 3 m and a recovery operation rec is performed for 100 &mgr;s, sequentially. From the drawing, it can be seen that a 0 bit line I/O-0; A and a F bit line I/O-15; B, being edge portions of the sector, have a large amount of bit line leak current.
Thus, conventionally, if the entire source lines are not uniformly charged-up since the charges are concentrated on the ends of the source line, the cell in the edge portion of the sector is over-erased. Therefore, there is a problem that reliability of a device is degraded since the bit line leak current is increased.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a flash memory device, which can prevent concentration of charges on a cell, thus preventing over-erase to the cell and making uniform distribution of a threshold voltage over the cell array.
In order to accomplish the above object, a flash memory device according to the present invention is characterized in that it comprises a flash memory cell formed in a cell array region of a substrate in which the cell array region and an outside circuit region are defined, a source region and a drain region, a junction region formed in the outside circuit region, a first metal contact formed on the source region, second and third metal contacts formed on the junction region, a first metal line connecting the first metal contact and the second metal contact, a second metal line connected to the third metal contact, and a via hole formed on the second metal line.


REFERENCES:
patent: 5309012 (1994-05-01), Jex et al.
patent: 5756385 (1998-05-01), Yuan et al.
patent: 5761121 (1998-06-01), Chang

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