Flash memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518529, 36518533, 365218, 365226, G11C 1134, G11C 700

Patent

active

057743991

ABSTRACT:
The present invention relates to a flash memory device and is constructed in such a way that the memory cell blocks are sequentially selected according to the input of the erasing signal and the output voltage of the negative charge pump is supplied only to the selected memory cell block to prevent the degradation of the operational performance of the device due to excessive load applied to the output terminal of the negative charge pump at the time of erase operation. Therefore, the present invention relates to a flash memory device in which the magnitude of the load applied to the output terminal of the negative charge pump is effectively reduced and accordingly, the degradation of operational performance of the device can be prevented.

REFERENCES:
patent: 5384742 (1995-01-01), Miyakawa et al.
patent: 5399928 (1995-03-01), Lin et al.
patent: 5513146 (1996-04-01), Atsumi et al.
patent: 5612913 (1997-03-01), Cappelletti et al.

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