Flash memory controller having reduced pinout

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S191000, C711S103000, C711S005000

Reexamination Certificate

active

07978516

ABSTRACT:
Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.

REFERENCES:
patent: 5982664 (1999-11-01), Watanabe
patent: 6016560 (2000-01-01), Wada et al.
patent: 2005/0114587 (2005-05-01), Chou et al.
patent: 2005/0193161 (2005-09-01), Lee et al.
patent: 2005/0273560 (2005-12-01), Hulbert et al.
patent: 2006/0195650 (2006-08-01), Su et al.
patent: 2007/0076479 (2007-04-01), Kim et al.
patent: 2007/0081408 (2007-04-01), Kwon et al.
patent: 2007/0133312 (2007-06-01), Roohparvar
patent: 2007/0245061 (2007-10-01), Harriman
International Search Report and Written Opinion dated Mar. 18, 2009.

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