Flash memory circuit and method of operation

Details Flash memory circuit and method of operation Flash memory circuit and method of operation

1991-11-12

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

365218, 365900, G11C 800

Patent

active

052630030

ABSTRACT:
A memory circuit for storing words of data has two memory banks each formed by a plurality of memory devices connected in parallel. In a first mode, the memory circuit responds to an initial request for access and an address signal by reading data from a storage location in one of the memory banks. Subsequent requests for access to contiguous storage locations do not require an address signal, instead a control mechanism responds by generating an address to read data alternately from storage locations in the first and second memory banks. In a second mode, the memory circuit responds to every request for access to the memory circuit by enabling access to the first or second memory bank as indicated by an address which accompanied the request. The memory devices of a given bank are erased and programmed in parallel. However, when a given storage location is found to contain one or more bits that were not erased, another erase command is sent to only those memory devices associated with a bit that was not erased. Similarly, when a word of data has not been stored properly, only those memory devices which failed to store a bit are placed into the write state for another programming attempt.

REFERENCES:
patent: 4413319 (1983-11-01), Schultz et al.
patent: 4566082 (1986-01-01), Anderson
patent: 4691303 (1987-09-01), Churchward et al.
patent: 4881206 (1989-11-01), Kadono
patent: 4899310 (1990-02-01), Baba et al.
patent: 5012408 (1991-04-01), Conroy
patent: 5036493 (1991-07-01), Nielsen
patent: 5060145 (1991-10-01), Scheuneman et al.
Book entitled CMOS Memory Products, published in 1991 by Advanced Microdevices, Inc.

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