Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-02
2001-01-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06181601
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory, and more particularly, to a flash memory cell that uses a diode and double poly stack.
BACKGROUND OF THE INVENTION
The stack-gate ETOX-cell, one of the most popular cell structures for flash memories, is widely programmed by channel hot-electron (CHE) and erased by Fowler-Nordheim (FN) tunneling through the source side or the channel area.
The n-channel ETOX-cell is conventionally fabricated by a twin-well process or recently in a triple-well process as shown in FIG.
1
. The triple-well structure is typically used to protect cells from noises generated outside the deep n-well by reverse-biasing the deep n-well to p-well junction, e.g., the deep n-well is biased to the highest potential (Vcc) and the p-well is biased to the lowest potential (Vss). The n+ source is typically doubly implanted by As
75
(with a high dose of 3E15/cm
2
~1E16/cm
2
for the n+ junction) and P
31
(with a lower dose of ~1E14/cm
2
for the n-junction) so that the source junction can be biased at high voltage (e.g. ~12 v) during erase operation. The n+ drain is typically implanted by As only with a high dose (~1E16/cm
2
) and the drain side does not need the lightly-doped-drain (LDD) implant and spacer structure.
Note that the LDD structure is not useful in an ETOX-cell, although it is important in CMOS transistors for reducing electrical field during switching for lower hot-electron generation. The tunnel oxide (T
ox
) is typically 80-120 angstroms thick, the inter-poly dielectric (T
pp
) typically consists of thin oxide-nitride-oxide (ONO) layers. As an example, a typical ETOX-cell based on 0.35 um CMOS design rule has the following cell parameters: T
ox
~90 angstroms, T
pp
~160 angstroms (oxide equivalent thickness), and control-gate to floating-gate coupling ratio of ~0.8.
The ETOX-cell of
FIG. 1
is programmed by channel-hot-electrons (CHE). The bias for programming is typically: V
d
=7v, V
cg
=9 to 12 v, and V
s
=0 v. Under these bias conditions, there is a large channel current (~1 mA/cell) for hot electron generation near the channel surface of the drain. Hot electrons are injected into the floating-gate when the oxide energy barrier is overcome and when assisted by the positive control gate bias. After programming, the amount of net electrons on the floating-gate increases, which results in an increase of the cell threshold voltage (V
T
). The electrons in the floating-gate will remain for a long time (e.g. 10 years at room temperature), unless intentionally erased. The drawback of CHE programming is low injection efficiency and large power consumption during programming.
The cell is erased by Fowler-Nordheim (F-N) tunneling through the source side or the channel area. The bias during source side erase is typically: V
d
~0 v or floating, V
cg
~−5 v to 0 v, and V
2
=+9 to +12 v. This establishes a large electrical field (~10 Mv/cm) across the tunnel oxide between the floating-gate and source overlap area. Electrons on the floating-gate will tunnel into the source and be removed away. It is known that there is large gate induced drain leakage (GIDL) current that occurs at the source side during erase as well as the associated degradation of the tunnel oxide.
The bias for F-N erase through the channel area is typically: V
d
~floating, V
cg
~15 v, V
pw
~0 v. A large electrical field (−10Mv/cm) can be established across the tunnel oxide between the floating-gate and the p-well channel area (in accumulation). Electrons on the floating-gate will tunnel into the channel area and be removed through the p-well bias. It is well known that a high negative voltage is required on the control-gate and the tunnel oxide is easily degraded by the high electrical field during erase.
The read biases of the prior art ETOX-cell are typically: V
d
~1 v to 2 v, V
cg
~V
cc
, V
s
~0 v, V
pw
~0 v, V
dnw
=Vcc, and V
sub
~0 v. The channel may be inverted or not depending on the net electron charge stored on the floating-gate, and results in the on and off of the cell as measured by the read current I
read
representing the digital information of “1” or “0” stored in the cell.
Turning to
FIG. 2
, another prior art flash cell is shown that uses band-to-band tunneling induced hot electron (BBHE) generation and injection. The cell is a p-channel ETOX cell that only uses electrons tunneling through the tunnel oxide. This can avoid oxide degradation by hole injection. The bias for programming the p-channel cell is shown in FIG.
2
. Electrons are initially generated on the surface of the p+ drain by the known mechanism of band-to-band tunneling. They are further accelerated when flowing toward the n-well and gain energy through the electrical field in the p+
-well junction. Hot electrons as generated by junction high field and impact ionization can overcome the oxide barrier with the help of positive bias on the control gate and are injected onto the floating gate. The initial electrons on the p+ drain can also be injected to the floating gate by Fowler-Nordheim tunneling if the electrical field across the oxide is large enough (about 10 Mv/cm). In short, the drain current during programming is contributed by three components: hot electron injection to the floating gate, Fowler-Nordheim tunneling to the floating gate, and GIDL current to the n-well. Note that the BBHE mechanism can be implemented only on a p-channel cell.
Nevertheless, each of these prior art approaches have disadvantages regarding size, current drain, and/or implementation as an array. What is needed is a method for manufacturing a flash cell having the advantages of small cell size and easily implemented as an array.
SUMMARY OF THE INVENTION
A flash memory cell formed in a semiconductor substrate is disclosed. The cell comprises: a deep n-well formed within said substrate; a p+ drain region formed within said deep n-well; a floating gate formed above said n-well, said floating-gate separated from said substrate by a thin oxide layer, said floating gate formed adjacent to said p+ drain region; and a control gate formed above said floating gate, said floating gate and said control gate separated by a dielectric layer.
REFERENCES:
patent: 5912842 (1999-06-01), Chang et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Nelms David
Taiwan Semiconductor Manufacturing Corporation
Tran M.
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