Flash memory cell structure and operating method thereof

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185260, C365S185280, C365S185290, C365S185330, C257S314000, C257S315000, C257S316000, C257S320000, C257S321000, C257S322000, C257S326000

Reexamination Certificate

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07436707

ABSTRACT:
A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5416738 (1995-05-01), Shrivastava
patent: 6091644 (2000-07-01), Hsu et al.
patent: 2004/0065917 (2004-04-01), Fan et al.

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