Flash memory cell programming method and system

Static information storage and retrieval – Floating gate

Reexamination Certificate

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C365S185180, C365S185270

Reexamination Certificate

active

06894925

ABSTRACT:
A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.

REFERENCES:
patent: 6490205 (2002-12-01), Wang et al.
patent: 20030185055 (2003-10-01), Yeh et al.

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