Flash memory cell having multi-program channels

Details Flash memory cell having multi-program channels Flash memory cell having multi-program channels

2005-10-25

2005-10-25

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185330

Reexamination Certificate

active

06958939

ABSTRACT:
A flash memory cell of an EEPROM split-gate flash memory, the memory cell including a substrate having a plurality of active regions, and a floating gate structure disposed over the substrate. The floating gate structure extends across at least three of the active regions of the substrate such that the floating gate structure and the at least three active regions define at least two channel regions dedicated for programming.

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Vandana Verma and Andrew Swaneck, “Proposed On-Chip Test Structure To Quantify Trap Densities Within Flash Memories”, Proceedings of the 1996 IEEE International Workshop On Memory Technology, Design and Testing (MTDT '96), pp. 22-26.

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