Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-06-06
2006-06-06
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185330
Reexamination Certificate
active
07057940
ABSTRACT:
A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a spacer is set on the sidewall of the select gate; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; an inter-gate dielectric layer is set between the control gate and the floating gate; and a tunneling dielectric layer is set between the floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
REFERENCES:
patent: 6856546 (2005-02-01), Guterman et al.
patent: 6925007 (2005-08-01), Harari et al.
patent: 6934192 (2005-08-01), Tailliet et al.
Hsu Cheng-Yuan
Huang Min-San
Hung Chih-Wei
Wu Chi-Shan
Jiang Chyun IP Office
Le Thong Q.
Powerchip Semiconductor Corp.
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