Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2006-04-17
2009-02-03
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185170, C365S185110, C365S063000, C365S185020
Reexamination Certificate
active
07486555
ABSTRACT:
A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.
REFERENCES:
patent: 5023680 (1991-06-01), Gill et al.
patent: 5025494 (1991-06-01), Gill et al.
patent: 5043940 (1991-08-01), Harari
patent: 5095344 (1992-03-01), Harari
patent: 5159570 (1992-10-01), Mitchell et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5229632 (1993-07-01), Yoshikawa
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5422504 (1995-06-01), Chang et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5677872 (1997-10-01), Samachisa et al.
patent: 5736443 (1998-04-01), Park et al.
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5877980 (1999-03-01), Mang et al.
patent: 5887145 (1999-03-01), Harari et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5936887 (1999-08-01), Choi et al.
patent: 5943267 (1999-08-01), Sekariapuram et al.
patent: 5973352 (1999-10-01), Noble
patent: 5990514 (1999-11-01), Choi et al.
patent: 6013551 (2000-01-01), Chen et al.
patent: 6044017 (2000-03-01), Lee et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6069382 (2000-05-01), Rahim
patent: 6091102 (2000-07-01), Sekariapuram et al.
patent: 6091104 (2000-07-01), Chen
patent: 6093605 (2000-07-01), Mang et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6108239 (2000-08-01), Sekariapuram et al.
patent: 6127696 (2000-10-01), Sery et al.
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6214665 (2001-04-01), Sakui
patent: 6222227 (2001-04-01), Chen
patent: 6246607 (2001-06-01), Mang et al.
patent: 6291297 (2001-09-01), Chen
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6455889 (2002-09-01), Sakui
patent: 6472707 (2002-10-01), Takahashi
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6541815 (2003-04-01), Mandelman et al.
patent: 6563728 (2003-05-01), Kobayashi
patent: 6570214 (2003-05-01), Wu
patent: 6580120 (2003-06-01), Haspeslagh
patent: 6925007 (2003-08-01), Harari et al.
patent: 6703298 (2004-03-01), Roizin et al.
patent: 6762092 (2004-07-01), Yuan et al.
patent: 6807105 (2004-10-01), Ogura et al.
patent: 6853028 (2005-02-01), Kim et al.
patent: 6859394 (2005-02-01), Matsunaga et al.
patent: 6888755 (2005-05-01), Harari
patent: 6894339 (2005-05-01), Fan et al.
patent: 6894930 (2005-05-01), Chien et al.
patent: 6898121 (2005-05-01), Chien et al.
patent: 6936887 (2005-08-01), Harari et al.
patent: 6992929 (2006-01-01), Chen et al.
patent: 7038291 (2006-05-01), Goda et al.
patent: 7049652 (2006-05-01), Mokhlesi et al.
patent: 7075823 (2006-07-01), Harari
patent: 7303956 (2007-12-01), Harari
patent: 7341918 (2008-03-01), Harari et al.
patent: 2002/0014645 (2002-02-01), Kobayashi
patent: 2002/0102774 (2002-08-01), Kao et al.
patent: 2003/0006450 (2003-01-01), Haspeslagh
patent: 2003/0032241 (2003-02-01), Seo et al.
patent: 2003/0047774 (2003-03-01), Sugita et al.
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2003/0155599 (2003-08-01), Hsu et al.
patent: 2003/0227811 (2003-12-01), Sugiura et al.
patent: 2003/0232472 (2003-12-01), Wu
patent: 2004/0021171 (2004-02-01), Nishizaka
patent: 2004/0079988 (2004-04-01), Harari
patent: 2004/0165443 (2004-08-01), Harari
patent: 2006/0040052 (2006-02-01), Fang et al.
patent: 2006/0176736 (2006-08-01), Harari
patent: 2006/0202256 (2006-09-01), Harari
patent: 2006/0231885 (2006-10-01), Lee
patent: 2006/0291281 (2006-12-01), Wang et al.
patent: 2007/0243680 (2007-10-01), Harari et al.
patent: 0373698 (1989-12-01), None
patent: 1265289 (2002-12-01), None
patent: 1289023 (2003-03-01), None
patent: 360117783 (1985-06-01), None
patent: 06037328 (1994-02-01), None
patent: 410144807 (1998-05-01), None
patent: 20001083192 (2000-06-01), None
patent: 20010110917 (2001-04-01), None
patent: WO 2004/040583 (2004-05-01), None
patent: WO 2007/121343 (2007-10-01), None
“Twin MONOS Cell with Dual Control Gates” by Yutaka Hayashi et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123.
“Notification of Transmittal of the International Search Report or the Declaration”, corresponding PCT application No. PCT/US03/32383, International Searching Authority, European Patent Office, Mar. 24, 2004, 9 pages.
Suh et al., “A 3.3V 32Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1995, pp. 94-95, 305-306, 128-129 and 350.
Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device”, IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
Nozaki et al., “A 1-Mb EEPROM With MONOS Memory Cell for Semiconductor Disk Application”, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.
Choi et al., “A Novel Booster Plate Technology in High Density NAND Flash Memories for Voltage Scaling-Down and Zero Program Disturbance”, IEEE Symposium on VLSI Technology Digest of Technical Papers, 1996, pp. 238-239.
Kim et al., “Fast Parallel Programming of Multi-Level NAND Flash Memory Cells Using the Booster-Line Technology”, Symposium on VLSI Technology Digest of Technical Papers, 1997, pp. 65-66.
Choi et al, “A Triple Polysilicon Stacked Flash Memory Cell With Wordline Self-Boosting Programming”, IEEE, 1997, pp. 283-286.
Satoh et al., “A Novel Channel Boost Capacitance (CBC) Cell Technology with Low Program Disturbance Suitable for Fast Programming 4Gbit NAND Flash Memories”, IEEE Symposium on VLSI Technology Digest of Technical Papers, 1998, pp. 108-109.
Hsu, Cheng-Yuan et al., “Splite-Gate NAND Flash Memory at 120nm Technology Node Featuring Fast Programming and Erase,” IEEE 2004 Symposium on VLSI Technology Digest of Technical Papers, Jul. 2004, pp. 78-79.
Wolf, PhD., Stanley, “Silicon Processing for the VLSI Era, vol. 4-Deep-Submicron Process Technology,” Lattice Press, 2002, pp. 1-806.
EPO, “Office Action,” corresponding European Patent Application No. 03770742.9 on Nov. 3, 2006, 3 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 11/379,004 on Feb. 20, 2008, 14 pages.
EPO, “Office Action,” corresponding European Patent Application No. 03770742.9, dated Jun. 11, 2007, 6 pages.
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 11/379,012 on Aug. 10, 2007, 14 pages.
USPTO, “Office Action”, mailed in related U.S. Appl. No. 11/379,004 on May 30, 2008, 12 pages.
Wolf, “Silicon Processing for the VLSI Era, vol. 1-Process Technology,” Second Edition, copyright 2000, pp. 666-667, p. 742.
The China State Intellectual Property Office, “Office Action,” corresponding Chinese Patent Application No. 200380104733.X, mailed on Oct. 10, 2008, 3 pages (translation only.).
USPTO, “Notice of Allowance and Fee(s) Due,” mailed in related U.S. Appl. No. 11/379,004 on Oct.17, 2008, 13 pages.
Davis , Wright, Tremaine, LLP
Nguyen Viet Q
Sandisk Corporation
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