Flash memory cell array and method of programming, erasing and r

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518533, 36518527, 36518528, 36518529, 257317, G11C 1600

Patent

active

059826711

ABSTRACT:
The present invention discloses a flash memory array in which four memory cells formed on a silicon substrate having a double well structure hold a source region or a drain region in common so that the area occupied by contact holes can be minimized and integration of device can be enhanced.

REFERENCES:
patent: 4763299 (1988-08-01), Hazani
patent: 5243559 (1993-09-01), Murai
patent: 5406514 (1995-04-01), Yoneda
patent: 5413946 (1995-05-01), Hong

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