Flash memory cell and method to achieve multiple bits per cell

Details Flash memory cell and method to achieve multiple bits per cell Flash memory cell and method to achieve multiple bits per cell

2002-01-25

2003-09-30

Le, Thong (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185280, C365S185260

Reexamination Certificate

active

06628544

ABSTRACT:

BACKGROUND OF THE INVENTION
Density is a major consideration in fabrication of semiconductor memories. The cost of manufacture of a memory device is directly related to the amount of semiconductor real estate used in storing a bit of information on a semiconductor chip. Costs can be reduced by scaling feature size to place more transistors on a single substrate and thereby achieve high density. Another cost-saving technique that stores more data in a given device is Multi-Level Cell (MLC) technology. It further increases cell density by increasing the number of possible states associated with a memory cell. MLC technology allows a memory cell to store information corresponding to more than one bit. Consequently, four logical states from a selection of 2
N
states (N=2) can be stored in each cell. Each state corresponds to a two-bit data pattern 00, 01, 10 or 11. Eight logical states from a selection of 2
N
states (N=3) can be stored in each cell. Each state corresponds to a three-bit data pattern 000, 001, 010, 100, 011, 101, 110, or 111, and so on.
U.S. Pat. No. 5,553,020, entitled “Structure and Method for Low Current Programming of Flash EEPROMS,” by Stephen N. Keeney and Gregory E. Atwood, and U.S. Pat. No. 5,515,317, entitled “Addressing Modes for a Dynamic Single Bit Per Cell to Multiple Bit Per Cell Memory,” by Steven E. Wells and Kurt B. Robinson are hereby incorporated by reference. Those patents indicate how EEPROM memories can be adapted to store multiple bits per cell. The Kenney et al. patent reports that its technique can place 64 (2
6
) different levels of voltage on the memory cells. However, one drawback of such devices is their continued reliance upon hot electron injection to program the cells. Such programming techniques have a narrow threshold distribution but they require high programming currents that make them unsuitable for portable equipment.
Conventional flash memories can be programmed by using hot electron injection or Fowler-Norheim (FN) tunneling and all are erased by FN tunneling. Hot electron injection is the conventional method of programming and Fowler-Norheim tunneling is the conventional method of erasure. Hot electron injection relies upon creating an avalanche of electrons beneath the floating gate. During programming, the control gate is biased to a high voltage to turn on the channel by creating an inversion layer beneath the gate. The source and substrate are held at ground. Next, the drain is biased to near Zener diode (pn junction) breakdown (about 0.5 volts below junction breakdown) to pinch off the channel. Electrons become “hot” (energetic) and accelerate toward the drain. Programming occur when the voltage on the floating gate Vfg exceeds 3.2V (Si/SiO2 energy barrier). Electrons are injected at the pinch-off region toward the floating gate by momentum transfer. In a typical hot electron programming operation the control gate is biased of about +12 volts and the drain is biased to about 6.5 volts.
Flash memory cells have enjoyed recent commercial success due to their relatively low cost, the ease in erasing information stored in a flash memory array and their applications to bank check cards, credit cards, and the like. A flash memory cell, which is recognized by the semiconductor industry as a standard, has not yet emerged. Existing flash memories embody different architectures. The programming, reading and erasing of cells can be generally described under one of the following architectures-NOR, AND, or NAND. Further, the programming mechanism of the flash memory cell typically involves Fowler-Nordheim tunneling through an energy barrier between the floating gate overlap and the drain/source region or electron injection over an energy barrier.
Hot electron injection is faster than Fowler-Norheim tunneling. However, hot electron injection also requires program currents higher than currents required for Fowler-Norheim programming. The additional current required for hot electron injection is a disadvantage for battery-operated systems because frequent programming rapidly depletes the energy stored the battery and requires a complex charge pump design to supply enough current during programming for portable system. This is especially critical for very small supplies, such as the batteries included in smart cards.
Flash memory arrays that operate with FN tunneling for erase mechanisms can involve floating gate-to-channel, floating gate-to-drain or floating gate-to-source as the charge clearing path from the floating gate. The floating gate to drain or source path is deleterious to erase operations and destroys the tunnel oxide area located between the floating gate overlap and the drain/source region. This is known as edge effect programming and it leads to a wide threshold voltage (Vt) distribution in large memory array, which is useless for MLC applications. Edge effect may damage or destroy the tunnel oxide through the programming mechanisms (e.g., programming a logic one or logic zero on the floating gate). These programming mechanisms can include charge carrier paths between the floating gate and drain or alternatively between the floating gate and source.
However, conventional cells do not include a programming operation involving a Fowler-Nordheim tunneling path between the channel and floating gate. Such an operation would be desirable because it could limit tunnel oxide damage or degradation because the electric field is distributed across the entire tunnel oxide region. This lessens the possibility of damage because the electric field in not concentrated at the edge but is distributed over the channel. This field re-distribution effect results in a narrow threshold voltage (Vt) distribution due to elimination of edge effect programming. Until now, a flash memory cell for NOR-type random access architectures, which allows uniform channel programming, has not existed. It would meet an unfilled need in the art to provide a NOR-type architecture with Fowler-Norheim tunneling for programming and erasing.
SUMMARY
The invention provides a programmable cell with triple well structure and a method of programming a flash memory array. In each cell there is a floating gate transistor. The triple well structure includes a substrate (third well) that has first and second wells. The first well is contained in the second well and the second well is of opposite polarity compared to the substrate and the first well. The first well comprises source and drain regions with a channel disposed between them. A floating gate insulating layer covers the channel and a floating gate electrode is on the floating gate insulator. An inter-gate insulator covers the floating gate electrode and is covered by a control gate electrode. A suitable voltage supply reverse biases the first well with respect to the second well. A uniform potential is applied to the channel via a programming voltage applied to the control gate electrode. The potential of the source region floats. The control gate voltage is adjusted to an intensity that is substantially uniform across the surface of the channel. As the voltage is increased, electrical charges tunnel through the floating gate oxide and are stored in the floating gate. Erasing is accomplished by reversing the process.
The structure and method may be practiced with either a one-transistor or a two-transistor cell and are compatible with P-MOS and N-MOS processes. The cells can be configured into NOR-type architectures. For a typical N-MOS floating gate transistor, the first p-type well is held at about −3 volts, the control gate is raised to about 12 to 13 volts and the source is allowed to float. For a P-MOS device, the first n-type well is held at about +3 volts and the control gate is lowered to about −12 to −13 volts and the source is allowed to float. The invention is capable of storing multiple different levels of charge in the floating gate.


REFERENCES:
patent: 5225362 (1993-07-01), Bergemont
patent: 5422845 (1995-06-01), Ong
patent: 5487033 (1996-01-01), Keeney et

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