Flash memory card

Static information storage and retrieval – Floating gate – Data security

Patent

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Details

36518511, 36518529, 36518533, 365218, 36523003, G11C 1300

Patent

active

056489293

ABSTRACT:
Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

REFERENCES:
patent: 5224070 (1993-06-01), Fandrich et al.
patent: 5267218 (1993-11-01), Elbert
patent: 5301161 (1994-04-01), Landgraf et al.
patent: 5341330 (1994-08-01), Wells et al.
patent: 5363334 (1994-11-01), Alexander et al.
Series 2 Flash Memory Cards, Oct. 1992, pp. 4-91, 4-95-4-96.

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