Flash memory array with independently erasable sectors

Details Flash memory array with independently erasable sectors Flash memory array with independently erasable sectors

2009-11-03

2011-11-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230060

Reexamination Certificate

active

08059470

ABSTRACT:
In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set of shared bitlines, a first row driver circuit is coupled to the set of word lines of the first subarray, and a second row driver circuit is coupled to the set of word lines of the second subarray. The first and second row driver circuits are operable to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray. The two row driver circuits are further operable to enable the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.

REFERENCES:
patent: 6788580 (2004-09-01), Takahashi

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