Flash memory array using adjacent bit line as source

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185110, C365S185190

Reexamination Certificate

active

11127466

ABSTRACT:
A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

REFERENCES:
patent: 5898616 (1999-04-01), Ono
patent: 5920503 (1999-07-01), Lee et al.
patent: 6028788 (2000-02-01), Choi et al.
patent: 6519181 (2003-02-01), Jeong
patent: 6654294 (2003-11-01), Jeong

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