Static information storage and retrieval – Floating gate – Disturbance control
Reexamination Certificate
2009-07-22
2010-12-07
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Floating gate
Disturbance control
C365S185030, C365S185150, C365S185140, C365S185110, C365S185230, C365S185260
Reexamination Certificate
active
07848140
ABSTRACT:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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Choi Steve
Hoang Loc B.
Hsueh Sheng-Hsiung
Ly Anh
Nguyen Hung Quoc
DLA Piper (LLP) US
Silicon Storage Technology, Inc.
Tran Andrew Q
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