Flash memory array system including a top gate memory cell

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185140, C365S185030

Reexamination Certificate

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07626863

ABSTRACT:
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

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