Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-03-12
2003-11-11
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S051000, C365S063000, C365S185060, C365S185170, C365S185260, C365S185300
Reexamination Certificate
active
06646914
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to programmable semiconductor memories, and more particularly, to the configuration of a memory device incorporating flash memory cells.
2. Cross-Reference to Related Case
This case is related to FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING, AND READING THEREOF, invented by Sameer Haddad, filed Dec. 11, 2001, Ser. No. 10/013,993.
3. Discussion of the Related Art
A type of programmable memory cell is commonly referred to as a flash memory cell. Such flash memory cell may include a source and a drain formed in a silicon substrate, or in a well that is formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer. A memory cell of this type is shown and described in U.S. Pat. No. 4,698,787, “Single Transistor Electrically Programmable Memory Device and Method”, issued to Mukheree et al. on Oct. 6, 1987.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell wile an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain. The high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate attracts the electrons floating through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during the read operation on the flash memory cell.
FIG. 1
illustrates what is known as a NOR memory array
100
. The array includes individual cells C
1
-C
16
made up of respective MOS field effect transistors T
1
-T
16
, each of the transistors including a source S, a drain D, a floating gate FG, and a control gate CG as described above, bit lines B
0
-B
3
, and word lines W
0
-W
3
. The cells are connected in an array of rows
102
,
104
,
106
,
108
and columns
110
,
112
,
114
,
116
, with the control gates of the cells in a row (for example row
104
) being connected to a respective word line (W
1
) and the drains of the cells in a column (for example column
114
) being connected to a respective bit line (B
2
). The sources of the cells in a column are connected together. It will be understood that
FIG. 1
shows only a small portion of the array, which portion is repeated to form the entire array.
A cell can be programmed by applying programming voltages of approximately 9-10 volts to the control gate, approximately 5 volts to the drain, and grounding the source. These voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of approximately 5 volts to the control gate, applying approximately 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bit line current will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one approach, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of −10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase the cell. Another method of erasing a cell is by applying 5 volts to the P well and −10 volts to the control gate while allowing the source and drain to float.
The array of
FIG. 1
is shown in layout form in FIG.
2
. The layout structure includes elongated, substantially parallel source/drain regions
120
,
122
,
124
,
126
, each made up of alternating sources S and drains D, a channel region CR connecting each adjacent source and drain as shown. Each bitline B
0
-B
3
is associated with a respective source/drain region
120
,
122
,
124
,
126
, running therealong and contacting the individual drains of its associated source/drain region by means of contacts
130
. The word lines of the structure are shown at W
0
-W
3
, and are orthogonal to the bit lines B
0
-B
3
. The sources S of the source/drain regions
120
,
122
,
124
,
126
are connected together in a direction parallel to the word lines W
0
-W
3
as shown in
FIG. 2
, being formed by a self-aligned-source (SAS) process as for example disclosed in U.S. Pat. No. 5,120,671, “Process For Self Aligning A Source Region With A Field Oxide Region And A Polysilicon Gate”, issued to Tangetal. on Jun. 9, 1992. Cells C
1
-C
16
are formed at the intersections of word lines W
0
-W
3
and bit lines B
0
-B
3
. Approximately every 20 bit lines across the array
100
, each self aligned source SAS is brought into contact with conductive lines CL running substantially parallel to the bit lines B
0
-B
3
by means of contacts
132
. The conductive lines CL are connected together by a connecting line
134
to which appropriate voltage Vss may be applied so that a common voltage may be applied to all the sources S.
The NOR architecture provides several advantages. With the ability to access each cell individually, a high level of drive current can be achieved so that the read speed is high. Furthermore, this architecture lends itself to reasonable device scaling, i.e., minimizing of the feature sizes, i.e., for example, minimizing of dimensions of active regions, isolation regions, word and bit lines.
However, such an architecture is subject to problems. For example, as described in U.S. Pat. No. 5,656,513, “Nonvolatile Memory Cell Formed Using Self-Aligned Source Implant” issued to Wang et al., issued Aug. 12, 1997 (assigned to the present Assignee), in the self-aligned-source process, a selective etch is undertaken to etch away tunnel oxide and field oxide between the word lines, this etch aligning with the edges of the word lines. While this etch is selective in that it etches the oxide at a much higher rate than the polysilicon word lines or silicon, it is not totally selective. Portions of the silicon of the source, as well as portions of the exposed polysilicon of the word lines, are etched away. The etch operate
Fastow Richard
Haddad Sameer
Advanced Micro Devices , Inc.
Elms Richard
Luu Pho
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