Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-08-27
2004-06-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S189050
Reexamination Certificate
active
06751121
ABSTRACT:
RELATED APPLICATIONS
This application claims priority to Italian Patent Application Serial No. RM2001A000516, filed Aug. 29, 2001, entitled “FLASH MEMORY ARRAY ARCHITECTURE,” and which is incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to flash memory array architecture.
BACKGROUND OF THE INVENTION
A flash memory is a type of non-volatile memory. That is, a flash memory is a type of memory that retains stored data without a periodic refresh of electricity. An important feature of a flash memory is that it can be erased in blocks instead of one byte at a time. Each erasable block of memory comprises a plurality of non-volatile memory cells (cells) arranged in rows and columns. Each cell is coupled to a word line, bit line and source line. In particular, a word line is coupled to a control gate of each cell in a row, a bit line is coupled to a drain of each cell in a column and the source line is coupled to a source of each cell in an erasable block. The cells are programmed and erased by manipulating the voltages on the word lines, bit lines and source lines.
Typically, flash memory integrated circuits include a primary or main array comprising a plurality of blocks of cells for storing external data and a secondary array of cells used to store operating parameters needed for operation of the flash memory. The types of data stored in the secondary array can include configuration bits to set the memory in a desired state at start up, engineering bits to store testing and manufacturing data, one time programmable (OTP) bits to store security and other customer data, trimming bits for the many analog functions of the memory, redundant bits to store memory addresses of defective rows and columns as well as redundancy columns and rows.
Traditionally, the secondary array is positioned along side the primary arrays in the integrated circuit in order to avoid discontinuities in the primary array. However, this type of architecture is quite cumbersome and requires the routing of many signal lines between the primary and secondary arrays. Moreover, interconnections in this architecture tend to waste a significant amount of silicon area as well as affect the overall speed of signals.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a flash memory architecture that reduces the size of the flash memory without impacting the speed of the flash memory.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory device is disclosed that includes a first and second bank. Each bank has a pair of quadrants of memory cells. Each quadrant further has a redundant fuse circuit to store operating parameters. Each redundant fuse circuit is coupled within an associated quadrant to reduce routing of signal lines. In addition, each quadrant has a sense amplifier circuit to read the memory cells.
In another embodiment, a non-volatile memory device comprises a memory array, a plurality of sense amplifiers, a plurality of data path circuitry and control circuitry. The memory array has two banks. Each bank has two quadrants of non-volatile memory cells. Moreover, each quadrant includes a plurality of non-volatile redundant fuses. There is a sense amplifier circuit for each quadrant of the memory array. The sense amplifier circuits are used to read the flash memory cells and the plurality of redundant fuses in each quadrant. Each of the data path circuitry is coupled to route data to and from each quadrant. The control circuitry is used to control memory operations to the memory array.
In another embodiment, a flash memory device comprises a first bank, a second bank and control circuitry. The first bank has a pair of quadrants of flash memory cells separated by a first row decoder circuit. The first row decode circuit is coupled to decode row address requests in the quadrants of the first bank. The second bank has a pair of quadrants of flash memory cells separated by a second row decoder circuit. The second row decoder circuit is coupled to decode row address requests in the quadrants of the second bank. Each quadrant is separated into individually erasable blocks of flash memory cells. Also included is a redundant fuse circuit for each quadrant. The redundant fuse circuit has a plurality of non-volatile redundant fuses that are used to store operating parameters that are used to operate an associated quadrant. A sense amplifier circuit is further included for each quadrant. Each sense amplifier circuit is coupled to read flash memory cells and non-volatile redundant fuses in the quadrants. In addition, there is a data path circuit for each quadrant to provide a data path to and from each quadrant. The control circuitry is used to control memory operations to the flash memory cells in the quadrants and the redundant fuses.
In another embodiment, a flash memory system comprises a memory array, a first and second row decoder, redundancy fuse circuits, sense amplifier circuits, data path circuitry, control circuitry and a processor. The memory array includes a first bank having a pair of quadrants of flash memory cells arranged in row and column fashion and a second bank having a pair of quadrants of flash memory cells arranged in row and column fashion. The first row decoder circuit is coupled to decode row address requests to the pair of quadrants in the first bank. The second row decoder circuit is coupled to decode row address requests to the pair of quadrants in the second bank. Each quadrant has a redundancy fuse circuit to store operating parameters. Moreover, each redundancy circuit is coupled within its associated quadrant to reduce routing of signals. A sense amplifier circuit is used for each quadrant. Each sense amplifier is coupled to read memory cells in its associated quadrant. A data path circuitry is used for each quadrant. The data path circuitry is used to transfer data to and from its associated quadrant. The control circuitry is used to control memory operations to the memory cells. The processor is coupled to provide external commands to the control circuitry and to receive and provide data to the data path circuitry.
A method of forming a flash memory comprising, separating a flash memory array into two banks of memory cells so the memory array can run two different memory operations concurrently, embedding redundant rows and redundant columns into each bank of the memory cells, embedding redundant fuse circuits to store operating parameters in the banks of memory cells to reduce the routing of signals and coupling sense amplifiers to the memory cells in the memory array and fuses in the redundant fuse circuit to read the memory cells and the operating parameters.
A method of operating a flash memory comprising, coupling regular columns of memory cells in a memory array into groups, wherein the columns within each group are selectively coupled to an associated sense amplifier, coupling redundant columns of memory cells embedded in the memory array into a redundant group, wherein the redundant columns in the redundant group are selectively coupled to a redundant sense amplifier and coupling an output of the redundant sense amplifier to a data path circuit to replace the output of a sense amplifier when an address request is to a defective column coupled to the sense amplifier.
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Hoang Huan
Leffert Jay & Polglaze P.A.
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