Static information storage and retrieval – Floating gate – Particular connection
Reissue Patent
1999-10-29
2001-10-23
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185230
Reissue Patent
active
RE037419
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the design and circuit structure of a flash memory, and more specifically to the layout of word line and source line decoders of a flash memory.
BACKGROUND OF THE INVENTION
In recent years, flash memory devices have been widely used in computer related equipment and other electronic appliances as storage devices. The nonvolatile and on-chip programmable capabilities of a flash memory are very important for storing data in many applications. As an example, flash memories are frequently used for the BIOS storage of a personal computer. In addition, the small physical size of flash memories also makes them very suitable for portable applications. Therefore, they have been used for storing programs and data for many portable electronic devices such as cellular phones, digital cameras and video game platforms.
Different from a normal random access memory (RAM) that can be randomly read, erased and programmed on a byte basis, a conventional EPROM-type flash memory features a byte-program and a block-erase capability with each block containing a number of bytes. Because the data within a memory block can not be selected for erasure individually, a flash memory has to erase the data of a whole block of memory cells, i.e., an erase block, and then program the new data byte by byte. The block erase scheme, however, not only is inflexible but also has an undesirable problem called over-erasure. The over-erasure results from the inherent difference between the speed of erasing of each memory cell. Because a large number of cells are erased together, the cells having the fast speed of erasing may be over-erased below 0V, while the cells having slow speed are not successfully erased yet. The over-erased cells will conduct leakage current and cause the malfunction of bit line (BL) sense amplifiers.
To add more flexibility for erasing memory cells, isolate non-selected memory cells and avoid disturbance of data, U.S. Pat. No. 5,548,551 provides a negative voltage decoder for erasing either one memory cell or a block of memory cells for a non-volatile memory. In practical applications, however, it is desired that a small (multiple bytes) and flexible (random and multiple word lines) erase size for the erase operation of a flash memory can be accomplished without any memory disturbance and over-erasure problems.
SUMMARY OF THE INVENTION
This invention has been made to overcome the above mentioned drawbacks of a conventional flash memory. The primary object of this invention is to provide a circuit structure that offers the capability of erasing memory cells on a small and flexible number of word lines of a flash memory. Another object of this invention is to provide a method of erasing a multiple number of word line pairs simultaneously as well as verifying each individual word line one at time. Yet another object of this invention is to provide a memory circuit structure and methods of operating the memory circuit to eliminate the memory disturbance and over-erasure problems that often occur in a conventional flash memory circuit. A further objects of this invention is to provide a source line circuit having segmented source lines so that the flash memory cells of a small segment in a word line can be erased without source disturbance. It is also an object of the invention to provide a new bias condition for erasing one of more segments in a word line and reduce the gate disturbance to non-selected segments. It is also another object of the invention to provide a novel erase operation flow to reduce the over-erasure and disturbance for achieving accurate memory cell's threshold voltage control.
The memory cells of the flash memory circuit of this invention are divided into a number of banks. The memory cells in each memory bank are organized as a plurality of rows and a plurality of columns. The sources of the memory cells of two adjacent rows are wired together and connected to a common source line. Each memory bank of this invention has its own word line decoder and source line decoder. The source line decoder has a source line latch associated with it for providing desired voltage levels under various memory operations. Address lines to the word line decoder and the source line decoder choose the selected word line and source line for memory operations.
In a first preferred embodiment, each word line decoder has both odd and even word line latches associated with it. For the erase operation, the preferred mode of operation of this invention is to select two adjacent word lines which share the common source line from each memory bank for erasing. When the memory cells of the two adjacent word lines are erased, negative voltages of around −10V can be applied through the word line latches to both word lines and a positive voltage such as 5V can be applied through the source line latch to provide an appropriate bias condition for the erase operation. When the memory cells are erase-verified, the word line under verification can be applied a verifying voltage through one word line latch while the other word line latch can provide a low voltage sufficient enough to cut off the over-erased memory cells on the other word line that is not under verification. Therefore, the false reading that usually exists in verifying a single word line is eliminated. In addition, each word line can be stopped erasing after being verified by applying appropriate voltage through its associated word line latch to reduce the over-erase problem. According to the embodiment, a multiple number of memory banks each having two word lines that share the same source line for erasing can be erased simultaneously with one erase operation. The erase size can be from a word line pair to a large number of multiple word line pairs.
In a second embodiment of this invention, there are also two latches associated with the decoder. One of the latches controls if the word line voltage of a selected memory row is provided by either the other latch or by the address lines. By supplying appropriate voltages to the address lines and the latches, a multiple pairs of word lines in a memory bank can be erased simultaneously and verified one by one properly. Nevertheless, if all the word lines in a memory bank are selected for erasing, any other memory bank can only have all its word lines erased or not at the same time because the address lines that may also provide word line voltages for this embodiment are shared by all memory banks. Therefore, for the erase operation, the preferred mode is to erase a multiple pairs of word lines less than the size of a memory bank in one erase operation or to erase a multiple memory banks simultaneously.
Two additional embodiments provide similar functions to the second embodiment are also disclosed. The third embodiment uses an additional latch for controlling how the word line voltage is supplied. With the additional latch, the device of a control circuit of the word line decoder can be better protected under certain conditions. The fourth embodiment which also uses an additional latch reduces the address lines required for both the word line decoder and the source line decoder to a half. The flexibility and preferred mode of operation for the two embodiments are the same as that of the second embodiment.
This invention also presents a source line circuit that allows the selection of the memory cells of a small segment in a row for erasing. By dividing the memory array of a memory bank into a number of segments each comprising a number of columns, the sources of the memory cells of two adjacent rows in a segment can be wired together to form a segmented source line. Each segmented source line on the same word line is connected to a shared source line through a source segment control transistor having a gate coupled to a source segment control line. Therefore, the memory cells on a word line can be erased segment by segment.
The source segment control lines and source segment control transistors of this invention provide better flexibility fo
Hsu Fu-Change
Lee Peter W.
Tsao Hsing-Ya
Aplus Flash Technology Inc.
Flehr Hohbach Test Albritton & Herbert LLP
Phan Trong
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