Static information storage and retrieval – Floating gate – Particular connection
Patent
1998-09-24
1999-09-14
Phan, Trong
Static information storage and retrieval
Floating gate
Particular connection
36518505, 36518523, G11C 1604, G11C 1606
Patent
active
059532505
ABSTRACT:
A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.
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Hsu Fu-Chang
Lee Peter Wung
Tsao Hsing-Ya
Aplus Integrated Circuits, Inc.
Phan Trong
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