Flash memory array and decoding architecture

Details Flash memory array and decoding architecture Flash memory array and decoding architecture

1997-06-05

1998-07-07

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

365 8522, 36518529, 36518533, 365218, G11C 1134, G11C 700

Patent

active

057779244

ABSTRACT:
A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminates over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

REFERENCES:
patent: 5200922 (1993-04-01), Rao
patent: 5546402 (1996-08-01), Niijima et al.
patent: 5671177 (1997-09-01), Ueki

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