Flash memory array and decoding architecture

Details Flash memory array and decoding architecture Flash memory array and decoding architecture

1997-06-30

1999-01-05

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518522, 36518529, 36518533, 365218, G11C 1134

Patent

active

058569421

ABSTRACT:
A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.

REFERENCES:
patent: 5422843 (1995-06-01), Yamada
patent: 5444655 (1995-08-01), Yoshikawa
patent: 5633822 (1997-05-01), Campardo et al.
patent: 5740107 (1998-04-01), Lee
patent: 5777924 (1998-07-01), Lee et al.

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