Flash memory architecture that utilizes a time-shared address bu

Details Flash memory architecture that utilizes a time-shared address bu Flash memory architecture that utilizes a time-shared address bu

1998-03-06

2000-01-18

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518529, 36518533, 36518904, G11C 1604

Patent

active

060162708

ABSTRACT:
A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is "free" for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.

REFERENCES:
patent: 5245572 (1993-09-01), Hosonocky et al.
patent: 5638323 (1997-06-01), Itano
patent: 5822244 (1998-10-01), Hansen et al.
AMD Publication #21357, "Am29DL800T/Am29DL800B, 8 Megabit (1MX8-Bit/512KX16-Bit), CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory", Rev. A, May 1997, pp. 1-38.

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