Flash memory architecture employing three layer metal interconne

Details Flash memory architecture employing three layer metal interconne Flash memory architecture employing three layer metal interconne

1999-08-23

2000-07-11

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365 63, G11C 810

Patent

active

060882875

ABSTRACT:
The present invention discloses a memory wordline decoder that includes a plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.

REFERENCES:
patent: 5410508 (1995-04-01), McLaury
patent: 5977799 (1999-11-01), Kai et al.
patent: 5978277 (1999-11-01), Hsu et al.

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