Flash memory architecture and method of operation

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185300, C365S189050, C365S230080

Reexamination Certificate

active

06288938

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memories and in particular to a novel flash memory array architecture and methods of operation of the same.
FIG. 1
is a simplified diagram of a conventional flash memory array. The array includes a matrix of flash memory cells
100
connected as shown to a group of bit lines BL
0
-BLM, a group of word lines WL
0
-WLN, and a common or global source line GSL that receives source voltage VSS. The most common variety of flash memories today employs channel hot electron (CHE) for programming and negative gated Fowler-Nordhiem (FN) tunneling for erase. The CHE programming normally programs 1, 2, 4, 8 or 16 cells at a time and involves multiple program and program verify steps. During the programming sequence voltages are applied to the various terminals of each cell until the cell threshold voltage VT rises above the minimum programming threshold voltage VTPmin. A typical condition for CHE programming of cell
00
is, e.g., word line
0
(WL
0
)=10volts, bit line
0
(BL
0
)=5 volts, WLI-N=0 volts, BL
1
-M=0 volts. This type of CHE programming can result in a well-controlled and narrow VTP distribution across the array.
Negative gated FN tunneling erase uses multiple erase and erase verify steps to ensure that the threshold voltage for all cells is less than the maximum erase threshold voltage (i.e., VT<VTEmax). As shown in
FIG. 1
, conventional flash memory arrays use a global source line GSL that connects to the source terminal of all cells within an array. Thus, during erase, all cells with a common source line are erased at the same time. This is commonly referred to as bulk erase or sector erase. A typical erase condition is, e.g., WL
0
-N=−10 volts, BL
0
-M=Float, and GSL (VSS)=4 volts. The negative gated FN tunneling erase in conventional flash memories suffers from a number of drawbacks. To ensure that the slowest cell in the array is fully erased, the erase operation normally involves multiple erase steps. In the case of those cells that are already erased prior to the start of another erase operation, a new erase cycle may cause the cell to be depleted, lowering the threshold voltage into the negative range. This effect, which is commonly referred to as over-erasure, can result in functional failure. To prevent over-erasure, all the cells in the array to be erased are first programmed before the actual erase operation begins. This is referred to as preprogramming. Preprogramming is a very time consuming process (e.g., 1 &mgr;s per cell) and increases the array erase time significantly.
Another problem with this type of bulk erase is poor control over VTE distribution. To increase the cell current and device speed, it is desirable to have a VTEmax that is as low as possible. Even with a preprogramming step, the simultaneous and repeated erasing of all of the cells in the array results in wide distribution of VTE among the cells across the array. A wide VTE distribution, however, places a lower limit on the value of VTEmax since VTEmin must not become negative.
FIG. 2
illustrates a typical distribution for VTE and VTP for a conventional FN-erase/CHE-program type flash memory. In this example, VTEmin is set at zero and VTEmax at 2 volts. There is a two volt sensing margin and a 1 volt data retention margin, placing VTPmin at 5 volts. With a 2 volt wide VTE distribution, targeting a lower VTEmax would result in negative VTEmin which would be unacceptable.
There is therefore a need for a flash memory device that does not suffer from the problems associated with over-erasure and wide VTE distribution.
SUMMARY OF THE INVENTION
The present invention provides a flash memory device that can be selectively erased, for example, on a bit-by-bit or page-by-page basis. Broadly, the flash memory according to the present invention includes latches that can be set or reset depending on cell content during erase verify. The flash architecture allows for bit-by-bit erase verify operation resulting in a tighter VTE distribution and elimination of the need for preprogramming. In one embodiment, a latch is connected to each bit line and includes a set/reset input that is controlled by a signal from the read sense amplifier output.
In a specific embodiment, instead of having a global source line, the flash memory according to the present invention divides the source line into multiple independent segments to reduce the potential leakage current that may otherwise result in read failure. More specifically, the source lines are divided by word line wherein, for example, one source line is shared by N adjacent word lines, where N (e.g., N=2) is determined based on process and application requirements. This reduces the number of memory cells attached to a bit line such that during read fewer potentially depleted cells would be attached to the bit line. In yet another embodiment, latches are placed on word lines instead of bit lines to allow for column erase with reduced bias voltage requirements. In a preferred embodiment, the flash memory cell according to the present invention is programmed by channel hot electron (CHE) tunneling and erased by FN tunneling, both occurring at the same (e.g., drain) junction.
Accordingly, in one embodiment, the present invention provides a flash memory device including: a plurality of memory cells arranged in a two-dimensional array of rows and columns; a plurality of latches respectively coupled to the columns of memory cells; a decoder coupled to the columns; and a sense amplifier having an input coupled to the decoder and an output coupled to a set/reset input of the plurality of latches, wherein the plurality of latches are selectively set or reset depending on the content of a selected cell. In an alternate embodiment, the plurality of latches couple to the rows.
In another embodiment, the present invention provides a method for erasing a flash memory device including the steps of: (a) selecting a memory cell to be erased; (b) reading cell current for the selected cell to determine a level of threshold voltage for the cell; (c) setting or resetting a state of a latch coupled to the selected memory cell depending on the level of the threshold voltage; and (d) erasing the selected memory cell by applying the state of the latch to the selected memory cell.
In yet another embodiment, the present invention provides a flash memory device including: a plurality of memory cells each having a gate terminal, a source terminal and a drain terminal, the memory cells being arranged in a plurality of rows and columns, wherein gate terminals of memory cells in each row couple to a respective word line, drain terminals of memory cells in each column couple to a respective bit line, and source terminals of the plurality of memory cells couple to a plurality of electrically separate source lines. In a specific embodiment, one of the plurality of electrically separate source lines couples to source terminals of memory cells in two adjacent rows.
In a further embodiment, the present invention provides a flash memory cell having a gate terminal, a source terminal coupled to a source region and a drain terminal coupled to a drain region, wherein programming of the cell occurs by biasing the memory cell to induce channel hot electron tunneling at one of the source or drain junctions, and erasing occurs by biasing the memory cell to induce FN tunneling at the same one of source or drain junctions where programming occurs.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the flash memory device and its method of operation according to the present invention.


REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4758986 (1988-07-01), Kuo
patent: 4884239 (1989-11-01), Ono et al.
patent: 4996571 (1991-02-01), Kume et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5357465 (1994-10-01), Challa

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