Static information storage and retrieval – Floating gate
Reexamination Certificate
1999-09-01
2001-11-13
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
C365S185290, C365S185330, C257S315000
Reexamination Certificate
active
06317360
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a flash memory as a non-volatile semiconductor memory device and more particularly to a novel structure thereof and a method of forming the same and methods of writing and erasing data.
DESCRIPTION OF THE RELATED ART
Conventionally, a flash memory capable of electrically writing and erasing informations has been known as a non-volatile semiconductor memory device.
FIG. 47
is a cross sectional view illustrative of a conventional structure of the flash memory. On a surface of a p-type silicon substrate
101
, source and drain regions
105
and
106
of n-type impurity diffusion layers. A floating gate
103
is formed via a gate oxide film
102
thereon and further a control gate
104
is laminated thereon.
The data writing and erasing to the flash memory may be carried out as follows.
In the erasure operation, for example, the drain region
106
is made into a floating state whilst the control gate
104
is grounded. The source region
105
is applied with, for example, a high voltage of about 12V. An F-N (Fowler-Nordheim) tunneling current flows through the gate oxide film
102
at overlapping portions between the source region
105
and the floating gate
103
. This F-N current extracts electrons from the floating gate
103
for carrying out the erasure.
In the writing operation, the source region
105
is grounded whilst the drain region
106
is applied with, for example, 7V and the control gate is applied with about 12V to cause an avalanche phenomenon in the vicinity of the drain region
106
under the floating gate edge, so that degenerated hot electrons are injected through the gate oxide film
102
in the drain side to the floating gate
103
from the silicon substrate
1
for carrying out the data write.
In reading operations, the source region
105
is grounded, whilst the drain region
106
is applied with, for example, 1V and the control gate is applied with about 3V, so that states “1” and “0” are judged depending upon a current higher than a predetermined value from the drain region
106
to the source region
105
, for carrying out the data reading operation. If the electrons are injected into the floating gate, then no current flows between the source and drain. In this case, the written state “1” is read. If electrons are extracted from the floating gate, then a current higher than the predetermined value flows between the source and drain. In this case, the read state “0” is read.
In the above examples, the state of electron extraction from the floating gate is set to be the erasure state whilst the other state of electron injection into the floating gate is set to be the written state. It is, however, possible that a bit-selectable operation is considered to be writing operation and a bit-unselectable operation is considered to be erasing operation. Namely, depending on the structure of the flash memory, the electron extraction may be considered to be writing operation.
For example, in AND-type cells, in
FIG. 47
(provided that a plan structure is different), in the write operation, the source region
105
is grounded or floated, whilst the drain region
106
is applied with 5V and the control gate
104
is applied with −9V to cause the F-N tunneling current whereby electrons are extracted from the floating gate. This is considered to be the data writing operation.
In the erasure operation, the source and drain regions
105
and
106
are grounded whilst the control gate
104
is applied with 18V to cause the F-N tunneling current flowing through the gate oxide film
102
between the source-drain channel region
108
and the floating gate
103
whereby electrons are injected into the floating gate. This is considered to be the data erasure operation.
It is necessary for the conventional flash memory to apply high voltage for erasure and writing operations. In order to reduce the voltage level, it may be considered to reduce the thickness of the gate oxide film. However, the reduction in thickness of the gate oxide film causes the gate oxide film to be deteriorated by frequent write and erase operations, whereby a leakage current so called to be stress induced leakage current may flow. This makes it difficult to store charges in the floating gate. It is possible that even application of a low field to the gate oxide film in the reading operation causes disturb-phenomenons or data erasure and data writing. It is no longer possible to keep reliability.
SUMMARY OF THE INVENTION
The present invention was made to solve the above problems. An object thereof is to provide a flash memory operable in low voltage with a high reliability without reduction in thickness of the gate oxide film.
A flash memory in accordance with the present invention is provided on a semiconductor substrate with: a trench with corners provided on a surface of the semiconductor substrate; a gate insulation film provided on a surface within the trench; a floating gate buried within the trench through the gate insulation film; and a control gate provided to be isolated from the floating gate, and also is characterized in that at the corners of the trench, corners of the floating gate face through the gate insulation film to edges of the semiconductor substrate, and if the control gate is made low potential whilst the semiconductor substrate is made high potential, then electrons are extracted from the corners of the floating gate.
In one practicable mode of the flash memory of the present invention, on the semiconductor substrate surface at the top corners of the trench, a thick insulating film is provided for preventing electron injections to the floating gate from the corners of the semiconductor substrate a the top edge of the trench.
In another practicable mode of the flash memory of the present invention, the floating gate is T-shaped with a wider portion than a trench width over the semiconductor substrate surface, and at the top edges of the trench, corners of the floating gate face through the gate insulation film to the edges of the semiconductor substrate, and if the control gate is made high potential whilst the semiconductor substrate is made low potential, then electrons are injected into the floating gate from the semiconductor substrate.
In this case, it is possible that a source region of a shallow impurity diffusion layer is provided on one side of the trench in the semiconductor substrate, whilst a drain region of such a deep impurity diffusion layer as to reach bottom corners of the trench is provided on an opposite side of the trench in the semiconductor substrate, and if the control gate is made low potential whilst the drain region is made high potential, then electrons are extracted from the floating gate to the drain region, and if the control gate is made high potential whilst at least any one of the source and drain regions is made low potential, then electrons are injected into the floating gate.
Alternatively, it is also possible that a drain region of such a deep impurity diffusion layer as to reach bottom corners of the trench is provided on an opposite side of the trench in the semiconductor substrate, whilst a source region of a shallow impurity diffusion layer is provided on one side of the trench and at a position separated from the floating gate, and further a select gate is provided between the floating gate and the source region.
A method of writing and erasing data of a flash memory in accordance with the present invention is characterized in that at least any one of writing and erasing operations is carried out by setting the semiconductor substrate at a high potential and also setting the control gate at a low potential to extract electrons from the floating gate.
In a method of writing and erasing data of a flash memory where corners of the floating gate face through the gate insulation film to the edges of the semiconductor substrate, it is possible that one of writing and erasing operations is carried out by setting the semiconductor substrate at a high potential and also setting the
Hoang Huan
NEC Corporation
Young & Thompson
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