Flash-erase-type nonvolatile semiconductor storage device

Details Flash-erase-type nonvolatile semiconductor storage device Flash-erase-type nonvolatile semiconductor storage device

1995-06-07

1996-08-13

Gordon, Paul P.

Excavating

371 401, 371 404, 36518509, 36518511, 36518517, 36518527, G11C 2900, G11C 1134

Patent

active

055464025

ABSTRACT:
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the invalidity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

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