Flash-erase-type nonvolatile semiconductor storage device

Details Flash-erase-type nonvolatile semiconductor storage device Flash-erase-type nonvolatile semiconductor storage device

1993-09-10

1996-04-16

Gordon, Paul P.

Excavating

36518517, 36518509, 36518527, 36518522, G06F 1100, G11C 1140

Patent

active

055090184

ABSTRACT:
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag area stores location information for defective memory cells in the corresponding data area. On the basis of this information, the system avoids the use of the defective memory cells. The defective memory cell information is programmed in a test step performed after chip manufacture and, at the same time, ECCs are generated for the defective memory cell information and written to the tag area. Furthermore, the system is informed of the validity of the data area that shares a word line with a tag area by writing predetermined data to the tag area. Even when the data area is erased en bloc, the tag area is not erased and the defective memory cell information is retained there.

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patent: 5200959 (1993-04-01), Gross et al.
patent: 5268870 (1993-12-01), Harari
patent: 5270980 (1993-12-01), Pathak et al.
patent: 5278793 (1994-01-01), Yeh
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IEEE Spectrum, Dec. 1989, "Flash Memories: The Best of Two Worlds" by Richard D. Pashley and Stefan K. Lai, Intel Corporation.

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