Static information storage and retrieval – Floating gate – Particular biasing
Patent
1992-06-22
1994-04-05
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
257300, 257313, 257315, 257316, G11C 1140
Patent
active
053011503
ABSTRACT:
A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor substrate as the control gate. One plate of the capacitor is formed from the same polysilicon layer as the floating gate of the memory device, thus capacitively coupling the floating gate and the inversion capacitor control gate. Additional erase performance is achieved by addition of a dedicated erase capacitor to the basic cell. Still further improvement in programming performance and protection against over-erase failure in a flash type EEPROM device is achieved by the addition of a select transistor. Prevention of program disturb and DC erase is also described.
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Mielke Neal R.
Sullivan Stephen F.
Intel Corporation
LaRoche Eugene R.
Le Vu A.
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