Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-12-05
1998-11-10
Yoo, Do Hyun
Static information storage and retrieval
Floating gate
Particular biasing
36518526, 36518527, 36518529, G11C 1606
Patent
active
058354085
ABSTRACT:
A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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Akaogi Takao
Kajita Tatsuya
Ogawa Yasushige
Watanabe Hisayoshi
Yamashita Minoru
Fujitsu Limited
Fujitsu VLSI Limited
Yoo Do Hyun
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