Flash erasable and programmable nonvolatile semiconductor memory

Details Flash erasable and programmable nonvolatile semiconductor memory Flash erasable and programmable nonvolatile semiconductor memory

1990-01-03

1990-10-30

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 357 235, G11C 1134

Patent

active

049673939

ABSTRACT:
In a nonvolatile semiconductor memory, each of a plurality of memory cells arranged in the form of a matrix includes a p-type semiconductor region, an n-type source connected to the ground potential, an n-type drain formed in a longitudinal direction with respect to the source, a channel region located between the source and the drain, a control gate transversely extending and formed above the channel region, intervening a first insulating film, a floating gate formed in the first insulating film above the channel region, and an erase gate formed in the first insulating film so as to spatially overlap one end of the floating gate. The memory further includes an erase line extending in the longitudinal direction, formed in the first insulating film and connected to the erase gate, and a data line, connected to the drain. First and second memory cells of the plurality of memory cells are arranged to be adjacent to one another in the transverse direction to constitute a first memory cell pair. The sources of the first and second memory cells are exclusively connected to one another. The sources of the adjacent memory cell series in the transverse direction are independently formed. The erase gate line connected to the erase gate and the source do not cross over each other.

REFERENCES:
patent: 4437172 (1984-03-01), Masuoka
patent: 4437174 (1984-03-01), Masuoka
patent: 4442092 (1983-12-01), Guterman
patent: 4466081 (1984-08-01), Masuoka
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4803529 (1989-02-01), Masuoka

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