Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-02-02
1997-01-21
Yoo, Do Hyun
Static information storage and retrieval
Floating gate
Particular biasing
36518511, 36518522, 3651853, 36518533, 365218, 36523003, G11C 700, G11C 1600
Patent
active
055965300
ABSTRACT:
A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.
REFERENCES:
patent: 5095461 (1992-03-01), Miyakawa et al.
patent: 5371702 (1994-12-01), Nakai et al.
patent: 5414664 (1995-05-01), Lin et al.
patent: 5428569 (1995-06-01), Kato et al.
Hsiao Ling-Wen
Lin Tien-Ler
Sung Gilbert
Wan Ray L.
Macronix International Co. Ltd.
Yoo Do Hyun
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