Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1998-06-26
2001-02-06
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185260
Reexamination Certificate
active
06185133
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to an erasing mechanism for flash EPROM devices. The invention is particularly useful for flash arrays because it is lower in cost to implement, has better convergence, and offers more functionality than traditional Fowler-Nordheim (FN) sector or bulk erase mechanisms.
BACKGROUND OF THE INVENTION
A typical prior art flash EPROM cell with a double poly stacked gate structure is illustrated in FIG.
1
. Such cell includes a source & drain region (one of which are typically connected to a common bit line), a control gate (poly 2 layer) an intergate dielectric (ONO layer), a floating gate (poly 1 layer) and a gate dielectric (tunnel oxide layer). A channel region lies between the gate dielectric and substrate, and runs lengthwise between the source/drain regions. In a conventional NOR based array architecture of such cells, hot-electron injection induced by a large channel electric field is used to charge the floating gate (poly 1 layer) in such cell. FN tunneling is used to discharge the floating gate, through the application of a large negative voltage to the control gate and a positive voltage to the source or substrate.
A known problem with using FN tunneling for an erase operation with such cell and array architectures is the possibility of an over-erase condition. This is an inevitable limitation resulting from a number of aspects of such architectures, including manufacturing variations, oxide layer wear, erase voltage fluctuations, etc. This condition arises when a threshold voltage V
t
of a cell becomes negative as a result of an erase operation performed in the EPROM. The over-erase condition of such cell leads to a number of well-known operational errors, and affects the scalability and reliability of this particular architecture. Consequently, significant research is expended in the field of flash EPROMs to develop cell structures and array operations that minimize the cell threshold variations therein.
Other problems associated with FN tunneling include the fact that such operations typically require two polarities of voltage, and this further necessitates the inclusion of a negative charge pump, thus increasing device size and complexity. Furthermore, manufacturing & processing complexity are relatively high with FN tunneling based EPROMs, since a triple well is also required to sustain the negative erase voltage. An example of such structure is seen in U.S. Pat. No. 5,491,657 to Haddad et. al., which is incorporated by reference herein. Finally, sophisticated embedded erase algorithms are also needed when using FN tunneling erase operations, and this further drives up the cost of such devices. While Haddad et. a indicate (column 6, 11. 44-50) that erasing of flash arrays using hot hole injection (rather than FN tunneling) is known in the art, Haddad et. al. also confirms that the approaches to date have had only limited success and utility since they yield widely varying threshold variations in the erased cells.
SUMMARY OF THE INVENTION
An object of the present invention, therefore, is to provide a circuit and method of erasing cells in a flash memory array that eliminates the need for a FN tunnelling operation in such array;
Another object of the present invention is to provide a circuit and method of erasing flash memory cells so that threshold voltage distributions of such cells are tightened, thereby increasing the functional performance of devices using such cells;
Yet another object of the present invention, is to provide a circuit and method of erasing cells in a flash memory array that improves device integration, cost and reliability by avoiding the use of erase support circuitry such as negative voltage charge pumps.
These and other objects are effectuated by a novel circuit and method for flash cell erasure disclosed in detail herein. A memory cell in a flash memory cell array (which cell typically includes a control gate, a floating gate, a source, a drain, a channel region between the source and drain, and a gate dielectric situated both between the floating gate and the source and drain, as well as between the channel and an associated substrate) is erased by first applying a positive erase voltage to either the source or drain of such cell, while the other of the source or drain regions is left floating. Only a single positive supply voltage is required, and this eliminates the need for bulky charge pumps. As a result of the fact that the substrate is also grounded, an avalanche condition occurs in a junction between the source/drain and substrate, and his creates a plasma of electron and hole pairs near the surface. The potential of the control gate is kept grounded or preferably slightly negatively biased, and this favors the attraction of positive charge carriers to move into the floating gate to erase the cell.
The present invention, therefore, can be incorporated within (and manufactured as part of) a conventional flash memory integrated circuit including a conventional array of flash memory cells and peripheral support circuitry coupled to the array. A constant current source generator capable of generating a specified current quantity I can be included as part of such peripheral circuitry. A control circuit coupled to the array and the peripheral support circuitry is configured to accomplish an erase operation using the method described immediately above. As the present invention does not require a programming operation first, an erase algorithm embedded in such circuit can be simplified significantly.
A constant current source is preferably used so that different positive erase voltages can be generated for cells having different operating characteristics. This approach ensures that variations in cell thresholds arising from different manufacturing/processing conditions, and different temperature conditions, are also handled without affecting performance.
As the cells are erased, their threshold voltages rapidly converge to a target value. After such target value is achieved, it does not vary substantially because an electric field in the gate dielectric is now balanced, and thus permits an approximately equal number of positive and negative carriers to move into the floating gate. This prevents the common problem of over-erasure typically present in prior art designs.
It can be seen that this method permits an entire sector of flash cells to be erased simultaneously, and without first pre-programming them to a known threshold voltage condition. This further reduces an erase time and makes the invention extremely attractive for use in flash memory cell chip architectures.
As the present invention does not utilize conventional Fowler-Nordheim tunnelling, over-erasure problems, processing complexity, and operating voltage logic complexity are also reduced significantly.
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Endoh, T. et al., “New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics,”IEDM, Apr. 1992, pp. 603-606.
Oyama, K. et al., “A Novel Erasing Technology for 3.3V Flash Memory with 64Mb Capacity and Beyond,”IEDM, Apr. 1992, pp. 607-610.
Miyawaki, Y. et al., “A New Erasing and Row Decoding Scheme for Low Supply Voltage Operation 16Mb/64Mb Flash EEPROMs,”Symposium on VLSI Circuits, 1991, pp. 85-86.
Chan Vei-Han
Chen Kou-Su
Liu David K. Y.
AMIC Technology, Inc.
Law+
Mai Son
LandOfFree
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