Flash EPROM integrated circuit architecture

Details Flash EPROM integrated circuit architecture Flash EPROM integrated circuit architecture

1994-10-26

1996-06-11

Ngo, Ngan V.

Static information storage and retrieval

Floating gate

36518902, 36518909, 36518533, 257316, H01L 29788

Patent

active

055263070

DESCRIPTION:

BRIEF SUMMARY
RELATED APPLICATION DATA

The present application is related to co-pending application entitled A FLASH EPROM TRANSISTOR ARRAY AND METHOD FOR MANUFACTURING THE SAME, filed on the same day as the present application, invented by Shone, et al., and owned by the same Assignee as the present application now and at the time of invention.


BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to flash EPROM memory technology, and more particularly to an improved flash EPROM memory architecture and data cell structure.
2. Description of Related Art
Flash EPROMs are a growing class of non-volatile storage integrated circuits. These flash EPROMs have the capability of electrically erasing, programming, and reading a memory cell in the chip. The memory cell in a flash EPROM is formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate or word line of the transistor by a second layer of insulating material.
Data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged through a Fowler-Nordheim tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected into the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate. When the floating gate is charged, the threshold voltage for causing the memory cell to conduct is increased above the voltage applied to the word line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by F-N tunneling mechanism between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate, while the drain is left at a floating potential.
The high voltages used to charge and discharge the floating gate place significant design restrictions on flash memory devices, particularly as the cell dimensions and process specifications are reduced in size.
Details concerning the structure and function of prior art flash EPROMs can be seen upon review of the following U.S. Patents which are incorporated by reference for the purpose of teaching the background of related technology: is set out in Belleza, European Patent Application No. 90104002.2, published Sep. 12, 1990; Woo, et al., "A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology" IEDM 1990, published by the IEEE, pages 91-94. Also, Woo, et al., "A Poly-Buffered "FACE" Technology for High Density Memories", 1991 SYMPOSIUM ON VLSI TECHNOLOGY, pages 73-74. One prior art "contactless" array EPROM architecture is described in Kazerounian, et al, "Alternate Metal Virtual Ground EPROM Array Implemented in A 0.8 .mu.M Process for Very High Density Applications", IEDM, published by IEEE 1991, pages 11.5.1-11.5.4.
As evidence by the Bergemont, et al., patent and the Belleza, Woo, et al., and Kazerounian, et al., publications, there is increasing interest in contactless array non-volatile memory design. So-called contactless arrays include an array of storage cells which are coupled to one another by buried diffusion, and the buried diffusion is only periodically coupled through contacts to a metal bit line. Earlier flash EPROM d

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