Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-11-16
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S052000
Reexamination Certificate
active
06219282
ABSTRACT:
TITLE OF THE INVENTION
A flash EPROM having means for increasing the reliability of stored data.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash EPROM, which can be rewritten electrically.
2. Description of the Prior Art
In the non-volatile memory semiconductor in the prior art, for example, a flash EPROM, it is reported that stored charges gradually discharge in a long time due to a minute defect in a memory cell. As a result, the stored data changes so that a data error occurs.
For avoiding the occurrence of such a data error, the non-volatile memory semiconductors in the prior art are screened before their shipment, and the reliability of data to be stored therein is guaranteed for a certain period of the utilization.
Some users, who use non-volatile memories, such as a flash EPROM, in a very hard condition, desire that data can be stored with high reliability at least in a certain memory area in the EPROM, and they admit the smallness of the memory size of such a high reliability memory area, if such reliability can be assured.
FIG. 10
is a block diagram of a flash EPROM in the prior art. The Flash EPROM comprises memory areas
101
-
103
, a selector
104
, a sense amplifier
105
, and word line decoders
106
-
108
for each of the memory areas
101
-
103
.
The function of the flash EPROM is explained below.
When the flash EPROM receives an address signal sent from an outer circuit, the word line decoders
106
-
108
decode the signal to select a word line, on the basis of the address signal.
The selector
104
selects a bit line. The data stored in the memory element at the crossing point of the bit line selected by the selector
104
and the word line selected by the word line decoders is read out by the sense amplifier
105
and is outputted to the outer circuit of the flash EPROM.
Each of the independent memory areas
101
-
103
in the non-volatile memory semiconductor in the prior art can independently write, store, and read data. However, means for verify whether the data read out from the memory areas
101
-
103
is correct or not is not equipped. Thus, there is a problem in the reliability of the read out data.
SUMMARY OF THE INVENTION
An object of the present invention is to eliminate the aforementioned problem.
Another object is to propose a flash memory having means for increasing the reliability of data read out from a memory element in the EPROM.
The objects are attained by a flash EPROM having means for increasing the reliability of read out data according to the present invention, comprising: a plurality of memory areas including a first and second memory area; sense amplifiers for the memory areas; a comparing means for comparing the data read out from the first and second memory areas; and a controlling means, which selects either of a normal mode for independent utilization of the first and second memory areas and a high reliability mode for simultaneous utilization of the first and second memory areas, wherein in the high reliability mode, the controller controls the first and second memory areas to store identical data, and controls the comparing means to compare the data read out from the first and second data areas, and to output the data to the outer circuit, when the read out data are identical to each other.
An embodiment of the flash EPROM of the present invention further comprises:
word line decoders, provided for each of the first and second memory areas, which decode address signals for selecting a memory element in each of the memory areas;
and a selector, provided for each of the first and second memory areas, which selects a bit line in each of the memory areas;
and said sense amplifier is provided for each of the first and second memory areas.
An embodiment of the flash EPROM of the present invention comprises a word line decoder provided commonly to the first and second memory areas, which decodes address signals for selecting a memory element in each of the memory areas,
and said sense amplifier is provided commonly for the first and second memory areas.
In an embodiment of the flash EPROM of the present invention, when the result of the comparison in the comparing means, in the high reliability mode, indicates that the data read out from the first and second memory areas do not coincide to each other, the comparing means outputs an error information to an outer circuit, which indicates that the data read out from the first and second memory areas do no coincide to each other.
In an embodiment of the flash EPROM of the present invention, when the result of the comparison in the comparing means, in the high reliability mode, indicates that the data read out from the first and second memory areas do not coincide to each other, the comparing means inverts either of the data read out from the first or second memory areas and outputs the inverted value, as a stored data, to an outer circuit.
In an embodiment of the flash EPROM of the present invention, said sense amplifier is provided commonly for a plurality of memory areas including the first and second memory areas.
In an embodiment of the flash EPROM of the present invention, the sense amplifier is provided for each of the first and second memory areas, and the threshold value of the inverter in the sense amplifier for either of the first and second memory areas is set higher than that of the inverters of the sense amplifier for the other memory areas.
In an embodiment of the flash EPROM of the present invention, the comparing means compares the data obtained through a sense amplifier having a higher threshold value and the data obtained through the other sense amplifier, and the controlling means refreshes the data in memory elements in the first and second memory areas, when the data obtained from the first and second memory areas do not coincide to each other.
According to an embodiment of the present invention, in the high reliability mode, an important data, for example, a program data, is stored redundantly in the first and second memory areas in a plurality of memory areas of the flash EPROM. The data stored in the first and second memory areas are sensed by a set of word line decoder, a selector and a sense amplifier, provided for each of the first and second memory area, and a set of comparing circuit and a switching controlling circuit provided commonly to these memory areas. When the data read out from theses memory areas coincide to each other, the data is judged to be correct, and the data is outputted to an outer circuit. When the data do not coincide to each other, the inverse of the data read out from either of the first and second memory areas is outputted to the outer circuit.
Thus, advantages can be obtained in that the reliability of data stored in the memory areas can be estimated, and the reliability of data can be improved.
According to another embodiment, an important data, for example, a program data, is stored redundantly in the first and second memory areas in a plurality of memory areas of the flash EPROM. The data stored in the first and second memory areas are sensed by a word line decoder provided to each of the first and second memory area, and a set of a selector, a sense amplifier, a comparing circuit and a switching controlling circuit provided commonly to these memory areas. The data stored in the first and second memory areas are read out alternately. When the data read out from these memory areas coincide to each other, the data is judged to be correct, and the data is outputted to an outer circuit. When the data do not coincide to each other, the inverse of the data read out from either of the first and second memory areas is outputted to the outer circuit.
Thus, advantages can be obtained in that the reliability of data stored in the memory areas can be estimated, and the reliability of data can be improved. Furthermore, the hardware can be simplified.
According to another embodiment, the threshold value of the inverter in the sense amplifier for a memory area is set higher than that of the inverters i
Burns Doane , Swecker, Mathis LLP
Le Thong
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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