Flash EEPROM with on-chip erase source voltage generator

Details Flash EEPROM with on-chip erase source voltage generator Flash EEPROM with on-chip erase source voltage generator

2001-01-23

2002-11-19

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290

Reexamination Certificate

active

06483750

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a Flash EEPROM with on-chip erase source voltage generator.
BACKGROUND OF THE INVENTION
It is known that Flash Electrically Erasable and Programmable Read Only Memories (shortly, Flash EEPROMs) have memory cells which are formed by floating-gate MOSFETs. Each floating-gate MOSFET comprises an N type source region and an N type drain region both formed in a spaced-apart condition in a P type semiconductor substrate. The portion of the P type substrate comprised between the source and drain regions forms a channel region, and a floating gate electrode is placed above the channel region with the interposition of a gate oxide layer having thickness of the order of 100 Angstroms. A control gate electrode is insulatively disposed over the floating gate electrode.
Flash EEPROM memory cell is written by means of injection of hot electrons from a portion of the channel region near the drain region into the floating gate. To activate hot-electron injection, the source region is normally grounded, the control gate electrode is biased with a voltage in the range 9-12 V and the drain region is biased with a voltage in the range 4-7 V. The negative charge trapped in the floating gate increases the threshold voltage of the floating-gate MOSFET, i.e. the minimum voltage that must be applied to the control-gate electrode to determine the formation of an N type inversion layer in the channel region.
Erasure of the Flash EEPROM memory cell is achieved by means of Fowler-Nordheim (F-N) tunneling of electrons from the floating gate to the source region through the gate oxide layer. To activate F-N tunneling, a sufficiently high electric potential difference between the source region and the floating gate must be created, to develop a strong electric field in the gate oxide layer. The known expression of the F-N current is:
I
F-N
=A*Eox
2
*exp
(
−B/Eox
)  (1)
where A and B are constants; Eox is the electric field in the gate oxide layer, given by:
Eox
=(
VS−VFG−
&PHgr;)/
Tox
  (2)
where VS is the electric potential applied to the source region, VFG is the electric potential of the floating gate (which is a function of the electric potential of the source and drain regions, of the substrate and of the control gate electrode, and of the charge trapped in the floating gate), &PHgr; is the voltage drop in the source region and Tox is the gate oxide layer thickness. The F-N current is a measure of the rate at which electrons are extracted from the floating gate: the higher the F-N current, the shorter the erasing time of the memory cell.
As known, in Flash EEPROMs all the memory cells, or at least large groups of them (called sectors), have their respective source regions tied to a common source line. The erasure is thus a global operation simultaneously involving a large number of memory cells.
According to a known technique, the electric potential difference between the source regions and the floating gates of the memory cells necessary to activate F-N tunneling is created by biasing the common source line of the memory cells to be erased with a voltage of approximately 12 V, and keeping the control gate electrodes grounded; the drain regions are instead left floating.
Actually, it is not possible to directly supply the source regions of the memory cells with the whole 12 V potential, because this would cause the junction between the source regions and the substrate (which is tied to ground) to break down. The electric potential actually applied to the source regions must thus be limited to a value suitable to not cause junction breakdown. This limits the F-N current, especially in the final phases of the erasure when the negative charge trapped in the floating gate has become small and its electric potential is less negative. As a consequence, the erasing time of the memory cells becomes quite long. Differently said, the erasing time of the memory cells is limited by the maximum voltage that can be applied to the source regions of the memory cells without causing the breakdown of the source regions-substrate junction.
Another drawback of this technique is that it imposes the use of an external power source for the 12 V potential, in addition to the usual 5 V (or 3 V) external power source. Even if breakdown of the source regions-substrate junction is prevented, the high reverse bias of this junction causes a significant leakage current to flow from the source regions to the substrate, which makes it impracticable the adoption of an on-chip charge pump for generating the 12 V potential.
According to another known technique, described for example in the co-pending European Patent Application No. 95830253.1 filed on Jun. 19, 1995 in the name of the same Applicant, the electric potential difference between the source regions and the floating gates of the memory cells necessary to activate F-N tunneling is created by applying to the control gate electrodes of the memory cells a negative voltage in the range −8 V to −12 V, generated directly on-chip by means of charge pumps, and connecting the common source line of the memory cells to be erased to the VCC pin of the Flash EEPROM. In this way, the source electrode bias voltage is provided by the VCC external supply, and the negative voltage for the control gate can be generated directly on-chip by means of charge pumps. The memory device thus requires a single external supply, i.e. the conventional VCC supply.
A feedback resistor is normally provided in series to the VCC pin and the common source line of the memory cells to be erased, for the reasons explained hereinafter.
The electric field in the gate oxide layer causes the energy bands at the surface of the source regions of the memory cells to bend; if the electric field is sufficiently high, the band bending exceeds the energy bandgap Eg of the semiconductor material (1.2 eV for silicon) and there is a finite probability for electrons in the valence band to tunnel into the conduction band. Electron-hole pairs are thus generated which give rise to a source-to-substrate current (Band-to-Band Tunneling current or BBT current). BBT current is given by:
 
I
BBT
=C*Esi
−2
*exp
(−
D/Esi
)  (3)
where C and D are constants and Esi is the electric field at the surface of the source regions of the memory cells, given by:
Esi
=(
VS−VFG−
1.2)/(3
*Tox
)  (4)
Equations (1)-(4) show that the F-N current and the BBT current depend in a similar way on the same parameters, so that if in the attempt to reduce the erasing time of the memory cells the F-N current is increased, also the BBT current increases. Moreover, the BBT current is normally several orders of magnitude higher than the F-N current. The feedback resistor allows to limit the source current of the memory cells during erasure, especially in its initial phases when, due to the negative charge trapped in the floating gate, Eox and Esi are maximum and there is a peak in the BBT current. The voltage drop across the feedback resistor, due to the BBT current, limits the electric potential of the source regions of the memory cells, thus limiting the BBT current.
The value of the feedback resistor is chosen on the basis of the maximum allowed source-to-substrate current. At the beginning of erasure, the voltage drop across the feedback resistor is maximum, then as electrons are extracted from the floating gate the potential of the floating gate raises, the electric field in the gate oxide layer decreases and the BBT current diminishes; the voltage drop across the feedback resistor also decreases, and the potential of the source regions of the memory cells raises toward the VCC value. In the final phases of erasure, when the BBT current is low, the potential of the source regions is substantially equal to VCC.
It can be shown that with the feedback resistor, even if the source voltage of the memory cells progressively approaches the VCC value, the electric field in the gate oxide layer of the

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