Flash EEPROM with erase verification and address scrambling arch

Details Flash EEPROM with erase verification and address scrambling arch Flash EEPROM with erase verification and address scrambling arch

1997-02-20

1999-11-23

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36518511, G11C 1606

Patent

active

059911956

ABSTRACT:
In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM.

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patent: 5297103 (1994-03-01), Higuchi
patent: 5347490 (1994-09-01), Terada
patent: 5396459 (1995-03-01), Arakawa
"A 60-ns 16 Mb Eeprom with Program and Erase Sequence Controller", IEEE Journal of Solid-State Circuits, Nov., 1991, No. 11, Nakayama et al.
"A 5V-Only 16 Mb Flash Memory with Sector-Erase Mode", IEEE International Solid-State Circuits Conference, Feb., 1992, Jinbo et al.
"A New Decoding Scheme and Erase Sequence for 5V Only Sector Erasable Flash Memory", 1992 Symposium on VLSI Circuits Digest of Technical Papers, Apr., 1992, Nakayama et al.

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