Flash EEPROM with controlled discharge time of the word lines an

Static information storage and retrieval – Floating gate – Particular biasing

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36518529, G11C 1134

Patent

active

057198071

ABSTRACT:
A Flash EEPROM having at least one memory sector. The memory sector includes a plurality of rows and columns of memory cells; at least one negative voltage generator for generating a negative voltage commonly charging the plurality of rows to a negative potential during an erase pulse for erasing the memory cells of the at least one memory sector and control logic activating the negative voltage generator at the beginning of the erase pulse and deactivating the negative voltage generator at the end of the erase pulse. The Flash EEPROM having for controlling a discharge time of the rows of the at least one memory sector at the end of the erase pulse.

REFERENCES:
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5416738 (1995-05-01), Shrivastava
patent: 5444655 (1995-08-01), Yoshikawa
patent: 5452248 (1995-09-01), Naruke
patent: 5485423 (1996-01-01), Tang
"Une seule tension de 5V pour la flash 16 Mbits," Electronique 2045(42):8, Nov. 1994.
Atsumi et al., "A 16-Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation ," IEICE Transactions on Electronics E77-C(5):791-798, May 1994.

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