Static information storage and retrieval – Floating gate – Particular connection
Patent
1994-09-09
1995-10-03
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular connection
257316, 257319, 257322, 257345, 257404, G11C 1604
Patent
active
054557925
ABSTRACT:
A flash electrically erasable programmable read only memory (EEPROM) device includes a two-dimensional array of single transistor non-volatile memory cells having the mid channel injection mechanism. The single transistor non-volatile memory cell includes a select gate, a control gate, and a floating gate which are disposed above a channel between a source and a drain. The control gate is located above the floating gate. In order to program the memory cell, the carrier injection into the floating gate is accomplished by the deflection of accelerated carriers from the middle region of the channel. Carriers are accelerated through the carrier acceleration passage by the horizontal component of the stray electric field, and deflected by the vertical component of the electric field. The erasure of memory cell is accomplished by the tunneling of carriers from the floating gate to the drain. Two types of array connection methods are proposed to optimize the flash mid channel injection EEPROM device either for high speed applications or for high density applications.
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