Static information storage and retrieval – Magnetic bubbles – Guide structure
Patent
1989-10-23
1992-06-30
Hille, Rolf
Static information storage and retrieval
Magnetic bubbles
Guide structure
357 45, 365185, 36518901, 365238, H01L 2978
Patent
active
051268086
ABSTRACT:
A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.
REFERENCES:
patent: 4371956 (1983-02-01), Maeda et al.
patent: 4458348 (1984-07-01), Fukuda et al.
patent: 4554646 (1985-11-01), Yoshimoto et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4723229 (1988-02-01), Hartgring et al.
patent: 4958321 (1990-09-01), Chang
R. Shirota, et al., "A 2.3 .mu.m Memory Cell Structure for 16Mb NAND EEPROMS," IEDM, pp. 5.4.1-5.4.4, (1990).
R. Kirisaw, "A NAND Structured Cell With a New Programming Technology for Highly Reliable 5V-Only Flash EEPROM," IEEE 1990 Symposium on VLSI Technology, pp. 129-130.
T. Tanaka, et al., "A 4-Mbit NAND-EEPROM with Tight Programmed V, Distribution," IEEE 1990 Symposium on VLSI Circuits, pp. 105 (1990).
Y. Itoh et al., "An Experimental 4Mb CMIS EEPROM with a NAND Structural Cell," Digest of Technical Papers, 1989 IEEE Int. Solid-State Circuits Conf., pp. 134-135, 314 (1989).
M. Momomodomi et al., "New Device Technologies for 5V-Only 4Mb EEPROM with NAND Structure Cell," IEDM, pp. 412-415 (1988).
F. Masuoka et al., "New Ultra High Density EPROM and Flash EEPROM with NAND Structure Cell," IEDM, pp. 552-555 (1987).
"A Five-Volt Contactless Array 256K Bit Flash EEPROM Technology", M. Gill et al., IEEE International Electron Devices Meeting, Dec. 11-14, 1988, pp. 428-430.
"Drain-Avalanche and Whole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices", Chi Chang et al., IEEE Electron Device Letters, vol. 9, No. 11, Nov. 1988, pp. 588-590.
"Corner-Field Induced Drain Leakage in Thin Oxide MOSFETs", Chi Change et al., IEEE International Electron Devices Meeting, Dec. 6-9, 1987, pp. 714-717.
"A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM", S. Mukherjee et al., IEEE International Electron Devices Meeting, 1985, pp. 616-619.
"A 128K Flash EEPROM Using Double-Polysilicon Technology", G. Samachisa et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
"Degradations Due to Hole Trapping in Flash Memory Cells", Sameer Haddad et al., IEEE Electron Device Letters, vol. 10, No. 3, Mar. 1989, pp. 117-119.
"A High Density CMOS 1-T Electrically Erasable Non-Volatile (Flash) Memory Technology", S. Tam et al., IEEE Electron Devices Society, 1988 Symposium on VLSI Technology Digest of Technical Papers, San Diego, CA May 10-13, 1988, pp. 31-32.
"A 5V-Only 256K Bit CMOS Flash EEPROM", S. D'Arrigo et al., 1989 IEEE International Solid-State Circuits Conference, Feb. 16, 1989, pp. 132-133, 313.
"A 1Mb Flash EEPROM", R.-A. Cernea et al., 1989 IEEE International Solid-State Circuits Conference, Feb. 16, 1989, pp. 138-139, 316.
"A 90ns 100K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., 1989 IEEE International Solid-State Circuits Conference, Feb. 16, 1989, pp. 140-141, 317.
"An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory Cell", Sameer Haddad et al., IEEE Electron Device Letters, vol. 11, No. 11, Nov. 1990, pp. 514-516.
"Look Out EPROMs, Here Comes Flash", Electronics, Nov. 1990, pp. 44-53.
"A 5 Volt Only 16M Bit Flash EEPROM Cell With a Simple Stacked Gate Structure", N. Ajkia et al. of Mitsubishi Electric Corp., IEDM, Dec. 1990, pp. 115-117.
"A Novel Sublithographic Tunnel Diode Based 5V-Only Flash Memory", Gill et al., of Texas Instruments, IEDM, Dec. 1990, pp. 119-122.
"Process Technology For A 5-Volt Only 4MB Flash EEPROM With An 8.6 UM2 Cell", Gill et al., of Texas Instruments, IEEE Symposium on VLSI Technology, Jun. 1990, pp. 125-126.
Montalvo Antonio J.
Van Buskirk Michael A.
Advanced Micro Devices , Inc.
Hille Rolf
Loke Steven
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