Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-01-05
1996-04-02
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518528, 36518518, 257390, 257500, 257505, G11C 1134
Patent
active
055047084
ABSTRACT:
In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.
REFERENCES:
patent: 5262985 (1993-11-01), Wada
patent: 5309402 (1994-05-01), Okazawa
D'Arrigo Sebastiano
Naso Giovanni
Santin Giovanni
Smayling Michael C.
Donaldson Richard L.
Heiting Leo N.
Lindgren Theodore D.
Nelms David C.
Niranjan F.
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