Flash EEPROM array with high endurance

Details Flash EEPROM array with high endurance Flash EEPROM array with high endurance

1993-05-06

1994-08-02

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 2900

Patent

active

053351983

ABSTRACT:
An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.

REFERENCES:
patent: 5122985 (1992-06-01), Santin
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5233562 (1993-08-01), Ong et al.
patent: 5237535 (1993-08-01), Melke et al.

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