Static information storage and retrieval – Floating gate – Particular biasing
Patent
1995-06-07
1997-01-28
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
36518529, 36518533, G11C 1700
Patent
active
055983693
ABSTRACT:
A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.
REFERENCES:
patent: 4630086 (1986-12-01), Sato et al.
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5341342 (1994-08-01), Brahmbhatt
patent: 5457652 (1995-10-01), Brahmbhatt
G. Samachisa et al., "A128K Flash EEPROM Using Double-Polysilicon Technology", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
C. Chang et al., "Drain-Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices", IEEE Electron Device Letters, vol. 9, No. 11, Nov. 1988, pp. 588-590.
Haddadad et al., "Degradatoins Due toHole Trapping in Flash Memory Cells", IEEE Electronic Device Letters, vol. 10, No. 3, Mar. 1989, pp. 117-119.
T. C. Ong et al., "Erratric Erase in ETOX.TM. Flash Memory Array", VLSI Symposium, 1992, pp. 83-84.
K. Yoshikawa et al., "Comprarison of Current flsh EEPROM Erasing Method: Stability and How to Control", IEDM, 1992, pp. 595-598.
K. Oyama et al., "A Novel Erasing Technology for 3.3V Flash Memory with 64 MB Capacity and Beyond", IEDM, 1992, pp. 607-610.
S. Aritome et al., "A Reliable Bi-Polarity Write/Erase Technology In Flash EEPROMs", IEDM, 1990, pp. 111-114.
C. Chang et al., "Corner-Field Induced Drain Leakage In Thin Oxide Mosfets IEDM", 1987, pp. 714-717.
A Bergemont, et. al; "NOR Virtual Ground (NVG)-A New Scaling Concept for Very High Density FLASH EEPROM and its Implementation in a 0.5um Process;" IEDM, Dec. 13, 1993, pp. 15-18.
R. Shirota, et. al; "A 2.3um square Memory Cell Structure for 16Mb NAND EEPROMs;" IDEM, Dec. 9, 1990, pp. 103-106.
Chen Jian
Radjy Nader
Advanced Micro Devices , Inc.
Le Vu A.
Nguyen Viet Q.
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