Flash E.sup.2 PROM array with mingle polysilicon layer memory ce

Details Flash E.sup.2 PROM array with mingle polysilicon layer memory ce Flash E.sup.2 PROM array with mingle polysilicon layer memory ce

1992-06-19

1994-10-25

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518908, 365 63, 365900, 257250, 257314, 257316, 257320, H03K 1921, G11C 1134

Patent

active

053595734

ABSTRACT:
In embodiments of flash E.sup.2 PROM arrays, an access transistor is included in each cell thereof, in series with the floating transistor of the cell, the access transistor being used to avoid the problem of drain disturbance in cells other than the cell being programmed. The connection of the control gates in certain of these arrays is such that gate disturbance on the floating gate transistors in those cells not being programmed is reduced or eliminated.

REFERENCES:
patent: 3952325 (1976-04-01), Beale et al.
patent: 4924278 (1990-05-01), Logie
patent: 4956564 (1990-09-01), Holler et al.
patent: 5099451 (1992-03-01), Sourgen et al.
patent: 5105386 (1992-04-01), Andoh et al.
H. Kume, et al, "A 1.28 .mu.m.sup.2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM", IEDM 1992 991-993 pp. 24.7.1 to 24.7.3.

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