Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-07-14
1994-10-18
LaRoche, Eugene R.
Static information storage and retrieval
Floating gate
Particular biasing
365218, G11C 700
Patent
active
053574664
ABSTRACT:
A Flash memory cell has a self-limiting erase to prevent over-erase and delivers a preset constant read current. The memory cell comprises first and second MOS transistors. The first and second transistors have a common source, first and second separate drains, a common floating gate and a common control gate. The first transistor has a higher threshold voltage than the second transistor. The cell is programmable by introducing a charge into the common floating gate. The cell is erasable by applying a voltage to the common source to discharge the floating gate. A feedback path is provided between the drain of the second transistor and the common control gate to limit the discharge to prevent over-erasing. The cell can be read by applying a read voltage to the common control gate. Because the erase is limited due to feedback, and there is no problem with over-erase, the threshold voltage of the first transistor is constant and known, and a preset constant read current is generated between the common source and the drain of the first transistor.
REFERENCES:
patent: 4317272 (1981-03-01), Kuo et al.
patent: 4797856 (1989-01-01), Lee et al.
patent: 5220528 (1993-06-01), Mielke
LaRoche Eugene R.
Nguyen Tan
United Microelectronics Corporation
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