Flash cell having self-timed programming

Static information storage and retrieval – Floating gate – Particular biasing

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36518521, G11C 1600

Patent

active

058525785

ABSTRACT:
A cell grid includes a plurality of cells in which at least one cell at a time is selected for programming. The programming cycle of each cell is self-timed so that once the actual programming process ends (i.e., an adequate number of electrons have injected through to the floating gate), programming is complete. Each cell in the cell grid has a source, a drain, a floating gate and a control gate. At least one bit line is included in the cell grid and is connected to the drains of corresponding cells including the selected cell. Further, at least one write line is included and is connected to the control gates of corresponding cells, so that one of the at least one write lines supplies a main voltage for maintaining the selected cell in an on-state during programming of the selected cell. At least one source line is included and is connected to the sources of each corresponding cell, so that one of the source lines supplies the necessary voltage required for programming of the selected cell and also supplies the main current source of the selected bit line during programming of the selected cell. An auxiliary transistor is coupled to each corresponding bit line and supplies an auxiliary current source to the selected bit line and maintains the remaining non-selected cells on the same selected bit line in the off-state during programming. A detection circuit is coupled to each corresponding auxiliary transistor and detects when the programming is complete by detecting a current source change between the main current and the auxiliary current source over time.

REFERENCES:
patent: 4794564 (1988-12-01), Watanabe
patent: 5200919 (1993-04-01), Kaya
patent: 5566111 (1996-10-01), Choi
patent: 5754472 (1998-05-01), Sim

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