Flash array implementation with local and global bit lines

Details Flash array implementation with local and global bit lines Flash array implementation with local and global bit lines

2005-09-06

2005-09-06

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230030, C365S230020, C365S230080, C365S231000, C365S185110, C365S185050, C365S185130

Reexamination Certificate

active

06940780

ABSTRACT:
A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

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