Flash array implementation with local and global bit lines

Details Flash array implementation with local and global bit lines Flash array implementation with local and global bit lines

2001-12-12

2004-09-21

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S230030, C365S230040, C365S230060

Reexamination Certificate

active

06795326

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to global and local bit line designs in synchronous non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas for computers. The term “memory” identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory, including RAM (random-access memory). RAM is typically used as main memory in a computer environment. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers can contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. An EEPROM (electrically erasable programmable read-only memory) is a special type of non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modem computers have their basic I/O system (BIOS) stored on a flash memory chip so that the BIOS can easily be updated when necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into erasable blocks. Each of the memory cells can be electrically programmed in a random basis by charging its floating gate. The charge can be removed from the floating gate using a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Semiconductor memories, including Flash memory, are commonly built using multi-layering wiring. These memories typically include hierarchical bit lines that are used to retrieve and write data into and from the memory array. The hierarchical bit lines generally include local bit lines and global bit lines. During the manufacture of a semiconductor memory on a wafer, shorts can occur between local bit lines as well as between global bit lines rendering the memory defective.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for efficiently testing a wafer for shorts in both local bit lines and global bit lines.
SUMMARY OF THE INVENTION
The above-mentioned problems with detecting bit line shorts in memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, the present invention provides a flash memory device that comprises, a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
In another embodiment, a flash memory device comprises a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. The plurality of select transistors each have a control gate and are coupled between the plurality of sets of adjacent local bit lines and the plurality of global bit lines. Moreover, every other local bit line in one of the plurality of sets of local bit lines is coupled to a different one of the plurality of global bit lines. A plurality of select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to every other global bit line.
In another embodiment, a flash memory device comprises, a plurality of local bit lines that are positioned generally parallel with each other, a plurality of select transistors and a plurality of global bit lines. Each select transistor has a control gate. Moreover, each select transistor is coupled to an associated one of the plurality of local bit line. Each global line is coupled to a pair of associated select transistors. The associated pair of select transistors are select transistors that are coupled to alternate local bit lines. In addition, the plurality of local bit lines comprise a first local bit line, a second local bit line, a third local bit and a fourth local bit line. A first select line coupled the control gates on the select transistors coupled to the first and second local bit lines. A second select line coupled to the select transistors coupled to the third and fourth local bit lines.
In another embodiment, a flash memory system comprises an array of flash memory cells, a plurality of local bit lines, a plurality of global bit lines and a select circuit. The memory cells of the array are arranged in rows and columns. The plurality of local bit lines are positioned generally parallel with each other and are coupled to an associated column of the memory array. Each global bit line is selectively coupled to a pair of associated local bit lines. The pair of associated local bit lines being the local bit lines that are alternately positioned with respect to each other. The select circuit selectively couples the local bit lines to the global bit lines. The plurality of local bit lines comprise a first local bit line, a second local bit line, a third local bit and a fourth local bit line. The select circuit comprises a select transistor for each local bit line. Each select transistor has a control gate. In addition, the flash memory system has a first select line and a second select line. The first select line is used to activate the control gates on the first and second local bit lines. The second select line is used to activate the control gates on the third and fourth local bit lines.
In another embodiment, a flash memory system comprises an array of flash memory cells, four local bit lines, a pair of global bit lines, a first multiplex circuit and a second multiplex circuit. The array of flash memory cells are arranged in rows and columns. The four local bit lines are positioned generally parallel with each other and comprise a first, second, third and fourth global bit line. Each local bit line is coupled to an associated column of flash memory cells. The first multiplex circuit is used to selectively couple a pair of associated local bit lines with an associated global bit line. The associated pair of local bit lines are local bit lines that are alternately positioned with respect to each other. The second multiplex circuit is used to selectively couple the remaining pair of local bit lines to the remaining global bit line. The associated pair of local bit lines are local bit lines that are alternately positioned with respect to each

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